Add ports to ilang for test_caller.py

diff --git a/src/soc/alu/test/test_pipe_caller.py b/src/soc/alu/test/test_pipe_caller.py
index d56019b293e569217a0982a74f16711037e61ee2..f42112e1805498a08b800aa50e8024dffdc5eb73 100644 (file)
--- a/src/soc/alu/test/test_pipe_caller.py
+++ b/src/soc/alu/test/test_pipe_caller.py
@@ -164,7 +164,7 @@ class ALUTestCase(FHDLTestCase):
 
         pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
         alu = ALUBasePipe(pspec)
-        vl = rtlil.convert(alu, ports=[])
+        vl = rtlil.convert(alu, ports=alu.ports())
         with open("pipeline.il", "w") as f:
             f.write(vl)
 

diff --git a/src/soc/branch/test/test_pipe_caller.py b/src/soc/branch/test/test_pipe_caller.py
index 335b63ed1890310966d41fd8caaaa38413c5bbe7..5f7a3fdd86677cf2dc0b369d0b89097953ae0446 100644 (file)
--- a/src/soc/branch/test/test_pipe_caller.py
+++ b/src/soc/branch/test/test_pipe_caller.py
@@ -103,7 +103,7 @@ class BranchTestCase(FHDLTestCase):
 
         pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
         alu = BranchBasePipe(pspec)
-        vl = rtlil.convert(alu, ports=[])
+        vl = rtlil.convert(alu, ports=alu.ports())
         with open("logical_pipeline.il", "w") as f:
             f.write(vl)
 

diff --git a/src/soc/cr/test/test_pipe_caller.py b/src/soc/cr/test/test_pipe_caller.py
index 1ce5b520989ef3d5609f3c3efe0dedb43bca37d3..10ede467bb8522490c37b0a6db84b811beeb2b46 100644 (file)
--- a/src/soc/cr/test/test_pipe_caller.py
+++ b/src/soc/cr/test/test_pipe_caller.py
@@ -89,7 +89,8 @@ class CRTestCase(FHDLTestCase):
 
         pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
         alu = CRBasePipe(pspec)
-        vl = rtlil.convert(alu, ports=[])
+        ports = alu.ports()
+        vl = rtlil.convert(alu, ports=alu.ports())
         with open("logical_pipeline.il", "w") as f:
             f.write(vl)
 

diff --git a/src/soc/logical/test/test_pipe_caller.py b/src/soc/logical/test/test_pipe_caller.py
index 190a9adeb6896c7027fd2f6836bc7eab991e0459..79c1e291b6d8ec1fa55d99ef82f8777832978c13 100644 (file)
--- a/src/soc/logical/test/test_pipe_caller.py
+++ b/src/soc/logical/test/test_pipe_caller.py
@@ -166,7 +166,7 @@ class LogicalTestCase(FHDLTestCase):
 
         pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
         alu = LogicalBasePipe(pspec)
-        vl = rtlil.convert(alu, ports=[])
+        vl = rtlil.convert(alu, ports=alu.ports())
         with open("logical_pipeline.il", "w") as f:
             f.write(vl)
 

diff --git a/src/soc/shift_rot/test/test_pipe_caller.py b/src/soc/shift_rot/test/test_pipe_caller.py
index 3244332bd97b209a3cf7f12e599643d9129496fa..dbd4092395cb85a3d3158c5047a14f1a76786ba2 100644 (file)
--- a/src/soc/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/shift_rot/test/test_pipe_caller.py
@@ -183,7 +183,7 @@ class ALUTestCase(FHDLTestCase):
 
         pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
         alu = ShiftRotBasePipe(pspec)
-        vl = rtlil.convert(alu, ports=[])
+        vl = rtlil.convert(alu, ports=alu.ports())
         with open("pipeline.il", "w") as f:
             f.write(vl)