update copyright notices to include additional primary author

(michael, please make sure to be properly informed on copyright law.
the git commit logs are the "ultimate" record, and simply being just one
of the authors does not mean that you can take the entire code and re-license
it under your own license.  you can only take the portions that *you* wrote)

diff --git a/src/soc/decoder/power_decoder.py b/src/soc/decoder/power_decoder.py
index 01af735293c22599b89899938e1d863bbffa754d..e4b87db1ca7debad7764c8318f222facd01f9914 100644 (file)
--- a/src/soc/decoder/power_decoder.py
+++ b/src/soc/decoder/power_decoder.py
@@ -1,5 +1,10 @@
 """Cascading Power ISA Decoder
 
+License: LGPLv3
+
+# Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+# Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
+
 This module uses CSV tables in a hierarchical/peer cascading fashion,
 to create a multi-level instruction decoder by recognising appropriate
 patterns.  The output is a wide, flattened (1-level) series of bitfields,
@@ -78,8 +83,6 @@ Top Level:
     ]
 
 
-Copyrights:
-# Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
 """
 
 from collections import namedtuple

diff --git a/src/soc/fu/branch/main_stage.py b/src/soc/fu/branch/main_stage.py
index 8a1b5f0ba0069063671c9bd7c7f23b683c56bab7..a8caa144b1905f2ba0cf51e79566d95894476527 100644 (file)
--- a/src/soc/fu/branch/main_stage.py
+++ b/src/soc/fu/branch/main_stage.py
@@ -1,3 +1,7 @@
+# License: LGPLv3
+# Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+# Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
+
 """Branch Pipeline
 
 This stage is intended to do most of the work of executing branch
@@ -23,7 +27,6 @@ Links:
 * https://bugs.libre-soc.org/show_bug.cgi?id=335
 * https://libre-soc.org/openpower/isa/branch/
 """
-# Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
 
 from nmigen import (Module, Signal, Cat, Mux, Const, Array)
 from nmutil.pipemodbase import PipeModBase

diff --git a/src/soc/fu/cr/main_stage.py b/src/soc/fu/cr/main_stage.py
index 36f587eb0b42b28e4f7dca3db765c64f21c31469..ac16f98972c6aab52511aa65b595070347bd04f5 100644 (file)
--- a/src/soc/fu/cr/main_stage.py
+++ b/src/soc/fu/cr/main_stage.py
@@ -1,3 +1,7 @@
+# License: LGPLv3
+# Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
+# Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+
 # This stage is intended to do Condition Register instructions (and ISEL)
 # and output, as well as carry and overflow generation.
 # NOTE: with the exception of mtcrf and mfcr, we really should be doing
@@ -8,7 +12,6 @@
 # own "Register File" (indexed by bt, ba and bb),
 # exactly how INT regs are done (by RA, RB, RS and RT)
 # however we are pushed for time so do it as *one* register.
-# Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
 
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
 from nmutil.pipemodbase import PipeModBase

diff --git a/src/soc/fu/shift_rot/main_stage.py b/src/soc/fu/shift_rot/main_stage.py
index 7d9dad09cb53362668fce85b43a43dc5c0c7c0fe..c0459874e9e370717d2483f446aa952ddb6f48ae 100644 (file)
--- a/src/soc/fu/shift_rot/main_stage.py
+++ b/src/soc/fu/shift_rot/main_stage.py
@@ -1,8 +1,11 @@
+# License: LGPLv3
+# Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
+# Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+
 # This stage is intended to do most of the work of executing shift
 # instructions, as well as carry and overflow generation. This module
 # however should not gate the carry or overflow, that's up to the
 # output stage
-# Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const)
 from nmutil.pipemodbase import PipeModBase
 from soc.fu.logical.pipe_data import LogicalOutputData

diff --git a/src/soc/simulator/gas.py b/src/soc/simulator/gas.py
index 14b2cd2c4e5d61d4f42e8bfe766ca8950180bf00..5e36a14f5f3ba60528c70396edf3ba15c9af64a5 100644 (file)
--- a/src/soc/simulator/gas.py
+++ b/src/soc/simulator/gas.py
@@ -1,7 +1,10 @@
+# License: LPGLv3
+# Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
+# Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+
 import tempfile
 import subprocess
 import struct
-# Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
 
 
 def get_assembled_instruction(instruction, bigendian=False):

diff --git a/src/soc/simulator/program.py b/src/soc/simulator/program.py
index 86cbf6b31a47be5ca286eb5a65853785ebf7218a..aeb33a23a170a893a0bcc4426a6bc2a774632790 100644 (file)
--- a/src/soc/simulator/program.py
+++ b/src/soc/simulator/program.py
@@ -1,9 +1,12 @@
+# License: LGPLv3
+# Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
+# Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+
 """POWER Program
 
 takes powerpc assembly instructions and turns them into LE/BE binary
 data.  calls powerpc64-linux-gnu-as, ld and objcopy to do so.
 """
-# Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
 
 import tempfile
 import subprocess