+# identifies register by type
+def is_CR_3bit(regname):
+ return regname in ['BF', 'BFA']
+
+def is_CR_5bit(regname):
+ return regname in ['BA', 'BB', 'BC', 'BI', 'BT']
+
+def is_GPR(regname):
+ return regname in ['RA', 'RB', 'RC', 'RS', 'RT']
+
+def get_regtype(regname):
+ if is_CR_3bit(regname):
+ return "CR_3bit"
+ if is_CR_5bit(regname):
+ return "CR_5bit"
+ if is_GPR(regname):
+ return "GPR"
+
+
+def decode_extra(rm, prefix=''):
+ # first turn the svp64 rm into a "by name" dict, recording
+ # which position in the RM EXTRA it goes into
+ # also: record if the src or dest was a CR, for sanity-checking
+ # (elwidth overrides on CRs are banned)
+ dest_reg_cr, src_reg_cr = False, False
+ svp64_srcreg_byname = {}
+ svp64_destreg_byname = {}
+ for i in range(4):
+ print (rm)
+ rfield = rm[prefix+str(i)]
+ if not rfield or rfield == '0':
+ continue
+ print ("EXTRA field", i, rfield)
+ rfield = rfield.split(";") # s:RA;d:CR1 etc.
+ for r in rfield:
+ rtype = r[0]
+ # TODO: ignoring s/d makes it impossible to do
+ # LD/ST-with-update.
+ r = r[2:] # ignore s: and d:
+ if rtype == 'd':
+ svp64_destreg_byname[r] = i # dest reg in EXTRA position 0-3
+ else:
+ svp64_srcreg_byname[r] = i # src reg in EXTRA position 0-3
+ # check the regtype (if CR, record that)
+ regtype = get_regtype(r)
+ if regtype in ['CR_3bit', 'CR_5bit']:
+ if rtype == 'd':
+ dest_reg_cr = True
+ if rtype == 's':
+ src_reg_cr = True
+
+ return dest_reg_cr, src_reg_cr, svp64_srcreg_byname, svp64_destreg_byname
+
+