yet more debug log stuff for DCache, this time on CacheRam, to discern

which SRAM the read/write request went to

diff --git a/src/soc/experiment/cache_ram.py b/src/soc/experiment/cache_ram.py
index 71dc89cac11286c77b1f448f29055e2db9b0127b..50ee1367cc84301bcf9cecf0f6cae51d13273227 100644 (file)
--- a/src/soc/experiment/cache_ram.py
+++ b/src/soc/experiment/cache_ram.py
@@ -4,7 +4,9 @@ from nmutil.util import Display
 
 class CacheRam(Elaboratable):
 
-    def __init__(self, ROW_BITS=16, WIDTH = 64, TRACE=True, ADD_BUF=False):
+    def __init__(self, ROW_BITS=16, WIDTH = 64, TRACE=True, ADD_BUF=False,
+                       ram_num=0):
+        self.ram_num = ram_num # for debug reporting
         self.ROW_BITS = ROW_BITS
         self.WIDTH = WIDTH
         self.TRACE = TRACE
@@ -33,8 +35,10 @@ class CacheRam(Elaboratable):
      
         with m.If(TRACE):
             with m.If(self.wr_sel.bool()):
-                sync += Display( "write a: %x sel: %x dat: %x",
-                                self.wr_addr, self.wr_sel, self.wr_data)
+                sync += Display( "write ramno %d a: %%x "
+                                 "sel: %%x dat: %%x" % self.ram_num,
+                                self.wr_addr,
+                                self.wr_sel, self.wr_data)
         for i in range(WIDTH//8):
             lbit = i * 8;
             mbit = lbit + 8;
@@ -43,7 +47,7 @@ class CacheRam(Elaboratable):
         with m.If(self.rd_en):
             sync += rd_data0.eq(ram[self.rd_addr])
             if TRACE:
-                sync += Display("read a: %x dat: %x",
+                sync += Display("read ramno %d a: %%x dat: %%x" % self.ram_num,
                                 self.rd_addr, ram[self.rd_addr])
                 pass
 

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 54981d75df79de04a366d30e5a8f90a9c273ccb2..072d34a90d108e601d0640930607ca205ab2fe4b 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -1124,7 +1124,7 @@ class DCache(Elaboratable):
             wr_sel_m = Signal(ROW_SIZE)
             _d_out   = Signal(WB_DATA_BITS, name="dout_%d" % i) # cache_row_t
 
-            way = CacheRam(ROW_BITS, WB_DATA_BITS, ADD_BUF=True)
+            way = CacheRam(ROW_BITS, WB_DATA_BITS, ADD_BUF=True, ram_num=i)
             setattr(m.submodules, "cacheram_%d" % i, way)
 
             comb += way.rd_en.eq(do_read)