add in SVSTATE to ISACaller, not used, just passed in

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 726fc638b76873359a8c5441d40c6415b3d71d06..41f129df80932bbea3c1bc562338922ceadeae56 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -425,7 +425,9 @@ class ISACaller:
 
         # set up registers, instruction memory, data memory, PC, SPRs, MSR
         self.svp64rm = SVP64RM()
-        self.svstate = SVP64State(initial_svstate)
+        if isinstance(initial_svstate, int):
+            initial_svstate = SVP64State(initial_svstate)
+        self.svstate = initial_svstate
         self.gpr = GPR(decoder2, self, self.svstate, regfile)
         self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
         self.imem = Mem(row_bytes=4, initial_mem=initial_insns)

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index a43f4a28405f19141cfea0aad40dc7bc86d8c966..8f190ca0625bf3b5e2bb06d1d58a83b43aed5ca6 100644 (file)
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -16,7 +16,9 @@ class Register:
     def __init__(self, num):
         self.num = num
 
-def run_tst(generator, initial_regs, initial_sprs={}):
+def run_tst(generator, initial_regs, initial_sprs=None, svstate=0):
+    if initial_sprs is None:
+        initial_sprs = {}
     m = Module()
     comb = m.d.comb
     instruction = Signal(32)
@@ -30,6 +32,7 @@ def run_tst(generator, initial_regs, initial_sprs={}):
     m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
     simulator = ISA(pdecode2, initial_regs, initial_sprs, 0,
                     initial_insns=gen, respect_pc=True,
+                    initial_svstate=svstate,
                     disassembly=insncode,
                     bigendian=0)
     comb += pdecode2.dec.raw_opcode_in.eq(instruction)

diff --git a/src/soc/decoder/isa/test_caller_svp64.py b/src/soc/decoder/isa/test_caller_svp64.py
index c9d1391a424b8e2e59e2ca5d170a068d4e46bf6c..34af4831a3d2e2cd10f44ac5c478a0dd6de85881 100644 (file)
--- a/src/soc/decoder/isa/test_caller_svp64.py
+++ b/src/soc/decoder/isa/test_caller_svp64.py
@@ -6,7 +6,7 @@ from soc.decoder.isa.caller import ISACaller
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_decoder2 import (PowerDecode2)
 from soc.simulator.program import Program
-from soc.decoder.isa.caller import ISACaller, inject
+from soc.decoder.isa.caller import ISACaller, SVP64State
 from soc.decoder.selectable_int import SelectableInt
 from soc.decoder.orderedset import OrderedSet
 from soc.decoder.isa.all import ISA
@@ -25,12 +25,17 @@ class DecoderTestCase(FHDLTestCase):
         initial_regs = [0] * 32
         initial_regs[3] = 0x1234
         initial_regs[2] = 0x4321
+        svstate = SVP64State()
+        svstate.vl[0:-1] = 2 # VL
+        svstate.maxvl[0:-1] = 2 # MAXVL
+        print ("SVSTATE", bin(svstate.spr.asint()))
         with Program(lst, bigendian=False) as program:
-            sim = self.run_tst_program(program, initial_regs)
+            sim = self.run_tst_program(program, initial_regs, svstate)
             self.assertEqual(sim.gpr(1), SelectableInt(0x5555, 64))
 
-    def run_tst_program(self, prog, initial_regs=[0] * 32):
-        simulator = run_tst(prog, initial_regs)
+    def run_tst_program(self, prog, initial_regs=[0] * 32,
+                              svstate=None):
+        simulator = run_tst(prog, initial_regs, svstate=svstate)
         simulator.gpr.dump()
         return simulator