add alternative pc_reset argument to issuer_verilog.py

which propagates right the way down to core.py
next to msr_reset it is now possible to set the pc_reset value.
these actually have to go into the regfile as initial values,
which will be fun for an ASIC

diff --git a/Makefile b/Makefile
index e89ad1d9fe5807c568a2d20e3d48a4f91a0bd1ca..f318ae315da4e8b0b21fe6d2ab1f44fdb9817c1a 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -63,6 +63,12 @@ microwatt_external_core:
        python3 src/soc/simple/issuer_verilog.py --microwatt-compat --enable-mmu \
             external_core_top.v
 
+microwatt_external_core_spi:
+       python3 src/soc/simple/issuer_verilog.py --microwatt-compat \
+            --enable-mmu \
+            --pc-reset 0x10000000 \
+            external_core_top.v
+
 # build the litex libresoc SoC without 4k SRAMs
 ls180_verilog_build: ls180_verilog
        make -C soc/soc/litex/florent ls180

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 0479508adf1e6aa915173a114966f97a1cd2702b..20a396c39000e52baca7ba47024df045db04262a 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -161,9 +161,12 @@ class NonProductionCore(ControlBase):
 
         # alternative reset values for STATE regs
         self.msr_at_reset = 0x0
+        self.pc_at_reset = 0x0
         if hasattr(pspec, "msr_reset") and isinstance(pspec.msr_reset, int):
             self.msr_at_reset = pspec.msr_reset
-        state_resets = [0x0,               # PC at reset
+        if hasattr(pspec, "pc_reset") and isinstance(pspec.pc_reset, int):
+            self.pc_at_reset = pspec.pc_reset
+        state_resets = [self.pc_at_reset,  # PC at reset
                         self.msr_at_reset, # MSR at reset
                         0x0,               # SVSTATE at reset
                         0x0,               # DEC at reset

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 4198ae26ff95a6ce25ec86f8b9c92b3249a77cad..1ddc42114ebef37adbfb113478ec2ffdaeb35274 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -59,6 +59,8 @@ if __name__ == '__main__':
     parser.add_argument("--disable-svp64", dest='svp64', action="store_false",
                         help="disable SVP64",
                         default=False)
+    parser.add_argument("--pc-reset", default=0,
+                        help="Set PC at reset (default 0)")
     parser.add_argument("--xlen", default=64, type=int,
                         help="Set register width [default 64]")
     # create a module that's directly compatible as a drop-in replacement
@@ -106,9 +108,15 @@ if __name__ == '__main__':
         ldst_ifacetype = 'bare_wb'
         imem_ifacetype = 'bare_wb'
 
-    # default MSR (TODO, provide option to set default PC as well)
+    # default MSR
     msr_reset = (1<<MSR.LE) | (1<<MSR.SF) # 64-bit, little-endian default
 
+    # default PC
+    if args.pc_reset.startswith("0x"):
+        pc_reset = int(args.pc_reset, 16)
+    else:
+        pc_reset = int(args.pc_reset)
+
     pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype,
                          imem_ifacetype=imem_ifacetype,
                          addr_wid=64,
@@ -133,7 +141,8 @@ if __name__ == '__main__':
                          microwatt_compat=args.mwcompat, # microwatt compatible
                          allow_overlap=args.allow_overlap, # allow overlap
                          units=units,
-                         msr_reset=msr_reset)
+                         msr_reset=msr_reset,
+                         pc_reset=pc_reset)
     #if args.mwcompat:
     #    pspec.core_domain = 'sync'
 
@@ -147,6 +156,8 @@ if __name__ == '__main__':
     print("debug", pspec.__dict__["debug"])
     print("SVP64", pspec.__dict__["svp64"])
     print("XLEN", pspec.__dict__["XLEN"])
+    print("MSR@reset", hex(pspec.__dict__["msr_reset"]))
+    print("PC@reset", hex(pspec.__dict__["pc_reset"]))
     print("Microwatt compatibility", pspec.__dict__["microwatt_compat"])
 
     if args.mwcompat: