for each unit test case in test_issuer_mmu_data_path.py initialise memory

to empty

diff --git a/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py b/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py
index 4742af0f2be31b6422142429bd5d40e7c2348091..f5919b9a9dc9bc050bda852b1128c85d8e2e5ead 100644 (file)
--- a/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py
+++ b/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py
@@ -13,12 +13,22 @@ class MMUTestCase(TestAccumulatorBase):
     # libre-soc has own SPR unit
     # other instructions here -> must be load/store
 
+    def cse_dcbz(self):
+        lst = [
+                "dcbz 1,2",
+              ]
+
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x2
+        initial_regs[2] = 0x2020
+
+        self.add_case(Program(lst, bigendian),
+                      initial_regs, initial_mem={})
+
     def case_mmu_dar(self):
         lst = [
-                 "mfspr 1, 720",     # DAR to reg 1
-                "addi 7, 0, 1",
+                "mfspr 1, 720",     # DAR to reg 1
                 "mtspr 19, 3",      # reg 3 to DAR
-                "mulli 7, 0, 1",
               ]
 
         initial_regs = [0] * 32
@@ -28,11 +38,11 @@ class MMUTestCase(TestAccumulatorBase):
         initial_sprs = {'DAR': 0x87654321,
                         }
         self.add_case(Program(lst, bigendian),
-                      initial_regs, initial_sprs)
+                      initial_regs, initial_sprs, initial_mem={})
 
-    def cse_mmu_ldst(self):
+    def case_mmu_ldst(self):
         lst = [
-                "dcbz 1,2",
+                "dcbz 1,0",
                 "tlbie 0,0,0,0,0", # RB,RS,RIC,PRS,R
                 "mtspr 18, 1",     # reg 1 to DSISR
                 "mtspr 19, 2",     # reg 2 to DAR
@@ -53,7 +63,7 @@ class MMUTestCase(TestAccumulatorBase):
         initial_sprs = {'DSISR': 0x12345678, 'DAR': 0x87654321,
                         'PIDR': 0xabcd, 'PRTBL': 0x0def}
         self.add_case(Program(lst, bigendian),
-                      initial_regs, initial_sprs)
+                      initial_regs, initial_sprs, initial_mem={})
 
 
 if __name__ == "__main__":

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 4629c4ed5f0bb896977c22e08e4c1ee28509b6b9..15642018b0e459836ae809e24ed1edc96a189af8 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -800,7 +800,11 @@ class FetchFSM(ControlBase):
                     comb += self.imem.f_i_valid.eq(1)
                 with m.Else():
                     # not busy: instruction fetched
-                    insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
+                    if hasattr(core, "icache"):
+                        # blech, icache returns actual instruction
+                        insn = self.imem.f_instr_o
+                    else:
+                        insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
                     sync += dec_opcode_o.eq(insn)
                     m.next = "INSN_READY"
                     # TODO: probably can start looking at pdecode2.rm_dec

diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index 56978f763d762e7b862331cdc62b8575fde9ac20..2daa86a5c5f8663151eb52a83d635e2282d5b8eb 100644 (file)
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -246,7 +246,7 @@ class HDLRunner(StateRunner):
             yield from setup_i_memory(imem, pc, instructions, self.dut.rom)
             yield from setup_tst_memory(l0, self.test.mem)
         else:
-            insert_into_rom(pc, instructions, self.dut.rom)
+            insert_into_rom(pc, instructions, self.dut.default_mem)
         print("about to setup regs")
         yield from setup_regs(pdecode2, core, self.test)
         #print("setup mem and regs done")