expose core_stop_i to outside as well

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index b7c38887946c65e08e7850eabaa74d2bc25ab07d..59b463b0a453e02391a38e82b629fff6e00e5686 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -49,6 +49,7 @@ class TestIssuer(Elaboratable):
         self.pc_o = Signal(64, reset_less=True)
         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
         self.core_start_i = Signal()
+        self.core_stop_i = Signal()
         self.core_bigendian_i = Signal()
         self.busy_o = Signal(reset_less=True)
         self.halted_o = Signal(reset_less=True)
@@ -74,6 +75,7 @@ class TestIssuer(Elaboratable):
         comb += self.busy_o.eq(core.busy_o)
         comb += self.halted_o.eq(core.core_terminated_o)
         comb += self.core_start_i.eq(core.core_start_i)
+        comb += self.core_stop_i.eq(core.core_stop_i)
         comb += self.core_bigendian_i.eq(core.bigendian_i)
 
         # temporary hack: says "go" immediately for both address gen and ST