whitespace

diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index e6345df73f14e8de8d3740bff7c93bea1c4ad8bc..1fd0f6577d3312c6693d1aaeef1aa48bb8559e2e 100644 (file)
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -131,7 +131,7 @@ class FSMMMUStage(ControlBase):
 
             with m.Switch(op.insn_type):
                 with m.Case(MicrOp.OP_MTSPR):
-                    comb += Display("MMUTEST: OP_MTSPR: spr=%i",spr);
+                    comb += Display("MMUTEST: OP_MTSPR: spr=%i", spr)
                     # despite redirection this FU **MUST** behave exactly
                     # like the SPR FU.  this **INCLUDES** updating the SPR
                     # regfile because the CSV file entry for OP_MTSPR
@@ -166,18 +166,18 @@ class FSMMMUStage(ControlBase):
 
                 with m.Case(MicrOp.OP_MFSPR):
                     comb += Display("MMUTEST: OP_MFSPR: spr=%i returns=%i",
-                                    spr,spr1_i);
+                                    spr, spr1_i)
                     comb += o.data.eq(spr1_i)
                     comb += o.ok.eq(1)
                     comb += done.eq(1)
 
                 with m.Case(MicrOp.OP_TLBIE):
-                    comb += Display("MMUTEST: OP_TLBIE: insn_bits=%i",spr);
+                    comb += Display("MMUTEST: OP_TLBIE: insn_bits=%i", spr)
                     # pass TLBIE request to MMU (spec: v3.0B p1034)
                     # note that the spr is *not* an actual spr number, it's
                     # just that those bits happen to match with field bits
                     # RIC, PRS, R
-                    comb += Display("TLBIE: %i %i",spr,l_out.done)
+                    comb += Display("TLBIE: %i %i", spr, l_out.done)
                     comb += valid.eq(1)   # start "pulse"
                     comb += l_in.valid.eq(blip)   # start
                     comb += l_in.tlbie.eq(1)   # mtspr mode