dcache.py add initial imports

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 0eb44c066058855568b19c9fdd5abb2a8f8de850..713299876369dd477cd92c8dbc6400b7e57298ac 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -1,3 +1,19 @@
+"""Dcache
+
+based on Anton Blanchard microwatt dcache.vhdl
+
+"""
+
+from nmigen import Module, Signal, Elaboratable,
+                   Cat, Repl
+from nmigen.cli import main
+from nmigen.iocontrol import RecordObject
+
+from experiment.mem_types import LoadStore1ToDcacheType,
+                                 DcacheToLoadStore1Type,
+                                 MmuToDcacheType,
+                                 DacheToMmuType
+
 # --
 # -- Set associative dcache write-through
 # --