- # rather than the client access the JTAG bus directly
- # create an alternative that the client sets
- dut.cbus = JTAGInterface()
-
- iotypes = (IOType.In, IOType.Out, IOType.TriOut, IOType.InTriOut)
- ios = [dut.add_io(iotype=iotype) for iotype in iotypes]
- dut.sr = dut.add_shiftreg(ircode=4, length=3) # test loopback register
-
- # create and connect wishbone SRAM (a quick way to do WB test)
- dut.wb = dut.add_wishbone(ircodes=[WB_ADDR, WB_READ, WB_WRRD],
- address_width=16, data_width=16)
- memory = Memory(width=16, depth=16)