add "nocore" option to build verilog

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 356e61985b295c156e1dde1d2f69ba87524a2aad..7fa96c0a3d8235e846f2ae8694212ce63ebae33d 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -120,6 +120,9 @@ class NonProductionCore(Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
+        # for testing purposes, to cut down on build time in coriolis2
+        if hasattr(self.pspec, "nocore") and self.pspec.nocore == True:
+            return m
         comb = m.d.comb
 
         m.submodules.fus = self.fus

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 820e5fd32ddfb3603efcd53b0639d1eb22080ff7..eec494af0094ff170318ab2afa8ff915f662ead1 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -28,6 +28,7 @@ if __name__ == '__main__':
                          # set to 32 to make data wishbone bus 32-bit
                          #wb_data_wid=32,
                          xics=True,
+                         nocore=True, # to help test coriolis2 ioring
                          gpio=False, # for test purposes
                          debug="jtag", # set to jtag or dmi
                          units=units)