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okaaay add a "rdflags" function which obtains the yes/no flags for each register...
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Mon, 1 Jun 2020 21:39:06 +0000
(22:39 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Mon, 1 Jun 2020 21:39:06 +0000
(22:39 +0100)
this to be used by the Decode phase
14 files changed:
libreriscv
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src/soc/fu/alu/pipe_data.py
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src/soc/fu/alu/pipeline.py
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src/soc/fu/branch/pipe_data.py
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src/soc/fu/branch/pipeline.py
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src/soc/fu/compunits/compunits.py
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src/soc/fu/compunits/test/test_compunit.py
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src/soc/fu/cr/pipe_data.py
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src/soc/fu/cr/pipeline.py
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src/soc/fu/logical/pipe_data.py
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src/soc/fu/logical/pipeline.py
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src/soc/fu/mul/pipeline.py
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src/soc/fu/shift_rot/pipe_data.py
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src/soc/fu/shift_rot/pipeline.py
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diff --git
a/libreriscv
b/libreriscv
index 6a79599c792e9271203c29082ee512a46930be85..041f868b620685068f375bce39c3aacf6aa986c4 160000
(submodule)
--- a/
libreriscv
+++ b/
libreriscv
@@
-1
+1
@@
-Subproject commit
6a79599c792e9271203c29082ee512a46930be85
+Subproject commit
041f868b620685068f375bce39c3aacf6aa986c4
diff --git
a/src/soc/fu/alu/pipe_data.py
b/src/soc/fu/alu/pipe_data.py
index cdd5c97a12e0876462caa7c25564ea3a1ca1d23b..33f54b026b95e06860a9f8b6a9a1b2797fdd59ee 100644
(file)
--- a/
src/soc/fu/alu/pipe_data.py
+++ b/
src/soc/fu/alu/pipe_data.py
@@
-1,4
+1,4
@@
-from nmigen import Signal, Const
+from nmigen import Signal, Const
, Cat
from soc.fu.alu.alu_input_record import CompALUOpSubset
from soc.fu.pipe_data import IntegerData, CommonPipeSpec
from ieee754.fpcommon.getop import FPPipeContext
from soc.fu.alu.alu_input_record import CompALUOpSubset
from soc.fu.pipe_data import IntegerData, CommonPipeSpec
from ieee754.fpcommon.getop import FPPipeContext
@@
-64,3
+64,7
@@
class ALUOutputData(IntegerData):
class ALUPipeSpec(CommonPipeSpec):
regspec = (ALUInputData.regspec, ALUOutputData.regspec)
opsubsetkls = CompALUOpSubset
class ALUPipeSpec(CommonPipeSpec):
regspec = (ALUInputData.regspec, ALUOutputData.regspec)
opsubsetkls = CompALUOpSubset
+ def rdflags(self, e): # in order of regspec
+ reg1_ok = e.read_reg1.ok # RA
+ reg2_ok = e.read_reg2.ok # RB
+ return Cat(reg1_ok, reg2_ok, 1, 1) # RA RB CA SO
diff --git
a/src/soc/fu/alu/pipeline.py
b/src/soc/fu/alu/pipeline.py
index 3a065b2e01b416182858b76a87a3f1e67118c103..a84efe1ef3629eb6f50cddfa21225bfc5ae43608 100644
(file)
--- a/
src/soc/fu/alu/pipeline.py
+++ b/
src/soc/fu/alu/pipeline.py
@@
-15,6
+15,7
@@
class ALUStages(PipeModBaseChain):
class ALUBasePipe(ControlBase):
def __init__(self, pspec):
ControlBase.__init__(self)
class ALUBasePipe(ControlBase):
def __init__(self, pspec):
ControlBase.__init__(self)
+ self.pspec = pspec
self.pipe1 = ALUStages(pspec)
self._eqs = self.connect([self.pipe1])
self.pipe1 = ALUStages(pspec)
self._eqs = self.connect([self.pipe1])
diff --git
a/src/soc/fu/branch/pipe_data.py
b/src/soc/fu/branch/pipe_data.py
index 4af59f3410c76cfac3b38bf3c492e17a75991437..a71c9dd17f52ae0decaca5607a7a838d8ad36dd3 100644
(file)
--- a/
src/soc/fu/branch/pipe_data.py
+++ b/
src/soc/fu/branch/pipe_data.py
@@
-23,7
+23,7
@@
op_bctarl CR, TAR, CTR
"""
op_bctarl CR, TAR, CTR
"""
-from nmigen import Signal, Const
+from nmigen import Signal, Const
, Cat
from ieee754.fpcommon.getop import FPPipeContext
from soc.decoder.power_decoder2 import Data
from soc.fu.pipe_data import IntegerData, CommonPipeSpec
from ieee754.fpcommon.getop import FPPipeContext
from soc.decoder.power_decoder2 import Data
from soc.fu.pipe_data import IntegerData, CommonPipeSpec
@@
-92,3
+92,8
@@
class BranchOutputData(IntegerData):
class BranchPipeSpec(CommonPipeSpec):
regspec = (BranchInputData.regspec, BranchOutputData.regspec)
opsubsetkls = CompBROpSubset
class BranchPipeSpec(CommonPipeSpec):
regspec = (BranchInputData.regspec, BranchOutputData.regspec)
opsubsetkls = CompBROpSubset
+ def rdflags(self, e): # in order of regspec
+ cr1_en = e.read_cr1.ok # CR A
+ spr1_ok = e.read_spr1.ok # SPR1
+ spr2_ok = e.read_spr2.ok # SPR2
+ return Cat(spr1_ok, spr2_ok, cr1_en, 1) # CIA CR SPR1 SPR2
diff --git
a/src/soc/fu/branch/pipeline.py
b/src/soc/fu/branch/pipeline.py
index 545b3435045aa436baf8cf83735abaaec81899be..1cdb3e9a1ff0c0c15219d84505e2c5bdce4d1122 100644
(file)
--- a/
src/soc/fu/branch/pipeline.py
+++ b/
src/soc/fu/branch/pipeline.py
@@
-11,6
+11,7
@@
class BranchStages(PipeModBaseChain):
class BranchBasePipe(ControlBase):
def __init__(self, pspec):
ControlBase.__init__(self)
class BranchBasePipe(ControlBase):
def __init__(self, pspec):
ControlBase.__init__(self)
+ self.pspec = pspec
self.pipe1 = BranchStages(pspec)
self._eqs = self.connect([self.pipe1])
self.pipe1 = BranchStages(pspec)
self._eqs = self.connect([self.pipe1])
diff --git
a/src/soc/fu/compunits/compunits.py
b/src/soc/fu/compunits/compunits.py
index d40549d5324dc50ef38e6ba88e1bca9a42dd6451..203055ad1cf3e3f1eabf0e80d93ad3157fe0c6c6 100644
(file)
--- a/
src/soc/fu/compunits/compunits.py
+++ b/
src/soc/fu/compunits/compunits.py
@@
-40,6
+40,7
@@
see:
"""
"""
+from nmigen import Cat
from nmigen.cli import rtlil
from soc.experiment.compalu_multi import MultiCompUnit
from nmigen.cli import rtlil
from soc.experiment.compalu_multi import MultiCompUnit
@@
-78,6
+79,10
@@
class FunctionUnitBaseSingle(MultiCompUnit):
note that it is through MultiCompUnit.get_in/out that we *actually*
connect up the association between regspec variable names (defined
in the pipe_data).
note that it is through MultiCompUnit.get_in/out that we *actually*
connect up the association between regspec variable names (defined
in the pipe_data).
+
+ note that the rdflags function obtains (dynamically, from instruction
+ decoding) which read-register ports are to be requested. this is not
+ ideal (it could be a lot neater) but works for now.
"""
def __init__(self, speckls, pipekls):
pspec = speckls(id_wid=2) # spec (NNNPipeSpec instance)
"""
def __init__(self, speckls, pipekls):
pspec = speckls(id_wid=2) # spec (NNNPipeSpec instance)
@@
-86,6
+91,10
@@
class FunctionUnitBaseSingle(MultiCompUnit):
alu = pipekls(pspec) # create actual NNNBasePipe
super().__init__(regspec, alu, opsubset) # pass to MultiCompUnit
alu = pipekls(pspec) # create actual NNNBasePipe
super().__init__(regspec, alu, opsubset) # pass to MultiCompUnit
+ def rdflags(self, e):
+ print (dir(self.alu))
+ return self.alu.pspec.rdflags(e)
+
##############################################################
# TODO: ReservationStations-based (FunctionUnitBaseConcurrent)
##############################################################
# TODO: ReservationStations-based (FunctionUnitBaseConcurrent)
@@
-112,6
+121,7
@@
class BranchFunctionUnit(FunctionUnitBaseSingle):
class ShiftRotFunctionUnit(FunctionUnitBaseSingle):
def __init__(self): super().__init__(ShiftRotPipeSpec, ShiftRotBasePipe)
class ShiftRotFunctionUnit(FunctionUnitBaseSingle):
def __init__(self): super().__init__(ShiftRotPipeSpec, ShiftRotBasePipe)
+
#####################################################################
###### actual Function Units: these are "multi" stage pipelines #####
#####################################################################
###### actual Function Units: these are "multi" stage pipelines #####
diff --git
a/src/soc/fu/compunits/test/test_compunit.py
b/src/soc/fu/compunits/test/test_compunit.py
index 08a704dc3165dfe746dc37b543118c93d8a88187..605b9127c1b1cf069d6b15a1c9d5c6536d9ac8d2 100644
(file)
--- a/
src/soc/fu/compunits/test/test_compunit.py
+++ b/
src/soc/fu/compunits/test/test_compunit.py
@@
-96,13
+96,6
@@
def get_inp_indexed(cu, inp):
res[i] = inp[wrop]
return res
res[i] = inp[wrop]
return res
-def get_cu_rd_mask(n_src, inp):
- mask = 0
- for i in range(n_src):
- if i in inp:
- mask |= (1<<i)
- return mask
-
class TestRunner(FHDLTestCase):
def __init__(self, test_data, fukls, iodef, funit):
class TestRunner(FHDLTestCase):
def __init__(self, test_data, fukls, iodef, funit):
@@
-160,7
+153,7
@@
class TestRunner(FHDLTestCase):
inp = get_inp_indexed(cu, iname)
# reset read-operand mask
inp = get_inp_indexed(cu, iname)
# reset read-operand mask
- rdmask =
get_cu_rd_mask(cu.n_src, inp
)
+ rdmask =
cu.rdflags(pdecode2.e
)
yield cu.rdmaskn.eq(~rdmask)
# reset write-operand mask
yield cu.rdmaskn.eq(~rdmask)
# reset write-operand mask
diff --git
a/src/soc/fu/cr/pipe_data.py
b/src/soc/fu/cr/pipe_data.py
index c22a3b1ecd19172eb2a898b1df2dbb29e6f1fcee..b16e56881bcc501982cb53faac459ab5e5cdefa5 100644
(file)
--- a/
src/soc/fu/cr/pipe_data.py
+++ b/
src/soc/fu/cr/pipe_data.py
@@
-2,7
+2,7
@@
Links:
* https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
"""
Links:
* https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
"""
-from nmigen import Signal, Const
+from nmigen import Signal, Const
, Cat
from ieee754.fpcommon.getop import FPPipeContext
from soc.fu.pipe_data import IntegerData, CommonPipeSpec
from soc.fu.cr.cr_input_record import CompCROpSubset
from ieee754.fpcommon.getop import FPPipeContext
from soc.fu.pipe_data import IntegerData, CommonPipeSpec
from soc.fu.cr.cr_input_record import CompCROpSubset
@@
-70,3
+70,11
@@
class CROutputData(IntegerData):
class CRPipeSpec(CommonPipeSpec):
regspec = (CRInputData.regspec, CROutputData.regspec)
opsubsetkls = CompCROpSubset
class CRPipeSpec(CommonPipeSpec):
regspec = (CRInputData.regspec, CROutputData.regspec)
opsubsetkls = CompCROpSubset
+ def rdflags(self, e): # in order of regspec
+ reg1_ok = e.read_reg1.ok # RA/RC
+ reg2_ok = e.read_reg2.ok # RB
+ full_reg = e.read_cr_whole # full CR
+ cr1_en = e.read_cr1.ok # CR A
+ cr2_en = e.read_cr2.ok # CR B
+ cr3_en = e.read_cr3.ok # CR C
+ return Cat(reg1_ok, reg2_ok, full_reg, cr1_en, cr2_en, cr3_en)
diff --git
a/src/soc/fu/cr/pipeline.py
b/src/soc/fu/cr/pipeline.py
index 050d0244e725ff94bb795b67bf2a3c96498d9bd3..af756eb105f8680dc7b2448260dac526aa3381a7 100644
(file)
--- a/
src/soc/fu/cr/pipeline.py
+++ b/
src/soc/fu/cr/pipeline.py
@@
-11,6
+11,7
@@
class CRStages(PipeModBaseChain):
class CRBasePipe(ControlBase):
def __init__(self, pspec):
ControlBase.__init__(self)
class CRBasePipe(ControlBase):
def __init__(self, pspec):
ControlBase.__init__(self)
+ self.pspec = pspec
self.pipe1 = CRStages(pspec)
self._eqs = self.connect([self.pipe1])
self.pipe1 = CRStages(pspec)
self._eqs = self.connect([self.pipe1])
diff --git
a/src/soc/fu/logical/pipe_data.py
b/src/soc/fu/logical/pipe_data.py
index 86e036226a091794d7001a8898918194d5cb73d5..ba24ce6d4bbf706d49c1a1c6f26d4b000053e770 100644
(file)
--- a/
src/soc/fu/logical/pipe_data.py
+++ b/
src/soc/fu/logical/pipe_data.py
@@
-1,4
+1,4
@@
-from nmigen import Signal, Const
+from nmigen import Signal, Const
, Cat
from ieee754.fpcommon.getop import FPPipeContext
from soc.fu.pipe_data import IntegerData
from soc.decoder.power_decoder2 import Data
from ieee754.fpcommon.getop import FPPipeContext
from soc.fu.pipe_data import IntegerData
from soc.decoder.power_decoder2 import Data
@@
-54,3
+54,7
@@
class LogicalOutputData(IntegerData):
class LogicalPipeSpec(CommonPipeSpec):
regspec = (LogicalInputData.regspec, LogicalOutputData.regspec)
opsubsetkls = CompLogicalOpSubset
class LogicalPipeSpec(CommonPipeSpec):
regspec = (LogicalInputData.regspec, LogicalOutputData.regspec)
opsubsetkls = CompLogicalOpSubset
+ def rdflags(self, e): # in order of regspec
+ reg1_ok = e.read_reg1.ok # RA
+ reg2_ok = e.read_reg2.ok # RB
+ return Cat(reg1_ok, reg2_ok) # RA RB
diff --git
a/src/soc/fu/logical/pipeline.py
b/src/soc/fu/logical/pipeline.py
index 4ae1d1d42b8d89382c2a8e81118dbb7ee1c42082..41aea1487347eb0d6dacd583f6abb72a76002ba0 100644
(file)
--- a/
src/soc/fu/logical/pipeline.py
+++ b/
src/soc/fu/logical/pipeline.py
@@
-15,6
+15,7
@@
class LogicalStages(PipeModBaseChain):
class LogicalBasePipe(ControlBase):
def __init__(self, pspec):
ControlBase.__init__(self)
class LogicalBasePipe(ControlBase):
def __init__(self, pspec):
ControlBase.__init__(self)
+ self.pspec = pspec
self.pipe1 = LogicalStages(pspec)
self._eqs = self.connect([self.pipe1])
self.pipe1 = LogicalStages(pspec)
self._eqs = self.connect([self.pipe1])
diff --git
a/src/soc/fu/mul/pipeline.py
b/src/soc/fu/mul/pipeline.py
index 2574517164094c5cd9da58e58da8c425fb3b1f3d..e726d170d79cf01c5af88454998f14ef60e46d6e 100644
(file)
--- a/
src/soc/fu/mul/pipeline.py
+++ b/
src/soc/fu/mul/pipeline.py
@@
-20,6
+20,7
@@
class MulStages2(PipeModBaseChain):
class ShiftRotBasePipe(ControlBase):
def __init__(self, pspec):
ControlBase.__init__(self)
class ShiftRotBasePipe(ControlBase):
def __init__(self, pspec):
ControlBase.__init__(self)
+ self.pspec = pspec
self.pipe1 = MulStages1(pspec)
self.pipe2 = MulStages2(pspec)
self._eqs = self.connect([self.pipe1, self.pipe2])
self.pipe1 = MulStages1(pspec)
self.pipe2 = MulStages2(pspec)
self._eqs = self.connect([self.pipe1, self.pipe2])
diff --git
a/src/soc/fu/shift_rot/pipe_data.py
b/src/soc/fu/shift_rot/pipe_data.py
index 7023a781e8fbb620bd20bc20281d5e1009e2d705..5c34a6921e942f60eaf189f448df3ad6972c32dd 100644
(file)
--- a/
src/soc/fu/shift_rot/pipe_data.py
+++ b/
src/soc/fu/shift_rot/pipe_data.py
@@
-1,4
+1,4
@@
-from nmigen import Signal, Const
+from nmigen import Signal, Const
, Cat
from nmutil.dynamicpipe import SimpleHandshakeRedir
from soc.fu.shift_rot.sr_input_record import CompSROpSubset
from ieee754.fpcommon.getop import FPPipeContext
from nmutil.dynamicpipe import SimpleHandshakeRedir
from soc.fu.shift_rot.sr_input_record import CompSROpSubset
from ieee754.fpcommon.getop import FPPipeContext
@@
-36,3
+36,8
@@
class ShiftRotInputData(IntegerData):
class ShiftRotPipeSpec(CommonPipeSpec):
regspec = (ShiftRotInputData.regspec, LogicalOutputData.regspec)
opsubsetkls = CompSROpSubset
class ShiftRotPipeSpec(CommonPipeSpec):
regspec = (ShiftRotInputData.regspec, LogicalOutputData.regspec)
opsubsetkls = CompSROpSubset
+ def rdflags(self, e): # in order of regspec input
+ reg1_ok = e.read_reg1.ok # RA
+ reg2_ok = e.read_reg2.ok # RB
+ reg3_ok = e.read_reg3.ok # RS
+ return Cat(reg1_ok, reg2_ok, reg3_ok, 1) # RA RB RC CA
diff --git
a/src/soc/fu/shift_rot/pipeline.py
b/src/soc/fu/shift_rot/pipeline.py
index 0449d37d964191fea1fb866f42292c201718100b..5121cb1e474cf561baf6a7edb8eb465ea024c3b8 100644
(file)
--- a/
src/soc/fu/shift_rot/pipeline.py
+++ b/
src/soc/fu/shift_rot/pipeline.py
@@
-15,6
+15,7
@@
class ShiftRotStages(PipeModBaseChain):
class ShiftRotBasePipe(ControlBase):
def __init__(self, pspec):
ControlBase.__init__(self)
class ShiftRotBasePipe(ControlBase):
def __init__(self, pspec):
ControlBase.__init__(self)
+ self.pspec = pspec
self.pipe1 = ShiftRotStages(pspec)
self._eqs = self.connect([self.pipe1])
self.pipe1 = ShiftRotStages(pspec)
self._eqs = self.connect([self.pipe1])