whoops setup of core.sv_pred_sm/dm not indented and under "if svp64_en"

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 0305624c3fd620b4c70906991beebe2907df4f4f..cd347aad0361497d7160267a052876f216ec6c5c 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -723,10 +723,10 @@ class TestIssuerInternal(Elaboratable):
                             # proceed to Decode
                             m.next = "DECODE_SV"
 
-                    # pass predicate mask bits through to satellite decoders
-                    # TODO: for SIMD this will be *multiple* bits
-                    sync += core.sv_pred_sm.eq(self.srcmask[0])
-                    sync += core.sv_pred_dm.eq(self.dstmask[0])
+                        # pass predicate mask bits through to satellite decoders
+                        # TODO: for SIMD this will be *multiple* bits
+                        sync += core.sv_pred_sm.eq(self.srcmask[0])
+                        sync += core.sv_pred_dm.eq(self.dstmask[0])
 
             # after src/dst step have been updated, we are ready
             # to decode the instruction