whoops fix up exception happened if alignment triggers from LoadStore1

set_wr_addr or set_rd_addr

diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index 2a3c85ae1a665cb26dd65e8b203c83f6ade125e9..15b2bfbd4141c80d9702f74071460b98b5b35094 100644 (file)
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -286,6 +286,9 @@ class LoadStore1(PortInterfaceBase):
             with m.If(self.mmu_set_dar):
                 sync += dar.eq(self.sprval_in)
 
+        # hmmm, alignment occurs in set_rd_addr/set_wr_addr, note exception
+        with m.If(self.align_intr):
+            comb += exc.happened.eq(1)
         # check for updating DAR
         with m.If(exception):
             sync += Display("exception %x", self.addr)