error in setting fast regs test values

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index e3c47eac011a68147cb8fedc6adb70d99da45a74..ff1ce52b24eb38e9c3531a6232600f6e8e5537cb 100644 (file)
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -119,9 +119,13 @@ def setup_regs(pdecode2, core, test):
                     else:
                         yield from set_mmu_spr(sprname, i, val, core)
         else:
-            yield fregs.regs[fast].reg.eq(val)
             print("setting fast reg %d (%s) to %x" %
                   (fast, sprname, val))
+            if fregs.unary:
+                rval = core.regs.int.regs[fast].reg
+            else:
+                rval = core.regs.int.memory._array[fast]
+            yield rval.eq(val)
 
     # allow changes to settle before reporting on XER
     yield Settle()