add isel CR tests to run on qemu (confirmed working)

diff --git a/src/soc/fu/cr/main_stage.py b/src/soc/fu/cr/main_stage.py
index ac16f98972c6aab52511aa65b595070347bd04f5..e81f77f7dbeaa9449b10b7159699504b063a5177 100644 (file)
--- a/src/soc/fu/cr/main_stage.py
+++ b/src/soc/fu/cr/main_stage.py
@@ -143,7 +143,7 @@ class CRMainStage(PipeModBase):
                 # just like in branch, CR0-7 is incoming into cr_a, we
                 # need to select from the last 2 bits of BC
                 a_fields = self.fields.FormA
-                BC = a_fields.BC[0:-1][0:2]
+                BC = a_fields.BC[0:2]
                 cr_bits = Array([cr_a[3-i] for i in range(4)])
 
                 # The bit of (cr_a=CR0-7) selected by BC

diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py
index 23d7a4f202f4e316c7b854f911e15aa36e213b3e..f428c9b2acfa369c8fb0ec5885a1952a7436d5b2 100644 (file)
--- a/src/soc/fu/cr/test/test_pipe_caller.py
+++ b/src/soc/fu/cr/test/test_pipe_caller.py
@@ -107,7 +107,7 @@ class CRTestCase(TestAccumulatorBase):
         for i in range(20):
             bc = random.randint(0, 31)
             lst = [f"isel 1, 2, 3, {bc}"]
-            cr = random.randint(0, (1 << 32)-1)
+            cr = random.randint(0, (1 << 64)-1)
             initial_regs = [0] * 32
             initial_regs[2] = random.randint(0, (1 << 64)-1)
             initial_regs[3] = random.randint(0, (1 << 64)-1)

diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index b461c7310226c1d51bf0c131b8ad6edd8494acad..17578632c4e174427bc12ca6db9267956b3d96a4 100644 (file)
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -299,7 +299,7 @@ if __name__ == "__main__":
     # suite.addTest(TestRunner(AttnTestCase.test_data))
     suite.addTest(TestRunner(GeneralTestCases.test_data))
     suite.addTest(TestRunner(LDSTTestCase().test_data))
-    # suite.addTest(TestRunner(CRTestCase().test_data))
+    suite.addTest(TestRunner(CRTestCase().test_data))
     # suite.addTest(TestRunner(ShiftRotTestCase.test_data))
     suite.addTest(TestRunner(LogicalTestCase().test_data))
     suite.addTest(TestRunner(ALUTestCase().test_data))

diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index 41c7e1d754338da55e7f02956bf0e5a80bfeb85e..680605b0c6a54a892874e779e2128930b2601a2a 100644 (file)
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -67,6 +67,7 @@ class GeneralTestCases(FHDLTestCase):
         """
         pass
 
+    @unittest.skip("disable")
     def test_0_litex_bios_cmp(self):
         """litex bios cmp test
         """
@@ -145,7 +146,7 @@ class GeneralTestCases(FHDLTestCase):
                                  [1, 2, 3],
                                  initial_mem)
 
-    #@unittest.skip("disable")
+    @unittest.skip("disable")
     def test_ldst_update(self):
         lst = ["addi 1, 0, 0x5678",
                "addi 2, 0, 0x1234",
@@ -170,7 +171,7 @@ class GeneralTestCases(FHDLTestCase):
         with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3])
 
-    #@unittest.skip("disable")
+    @unittest.skip("disable")
     def test_st_rev_ext(self):
         lst = ["addi 1, 0, 0x5678",
                "addi 2, 0, 0x1234",
@@ -243,6 +244,34 @@ class GeneralTestCases(FHDLTestCase):
         with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1])
 
+    def test_isel_1(self):
+        lst = ["addi 1, 0, 0x1004",
+               "addi 2, 0, 0x1008",
+               "addi 3, 0, 0x01ee",
+               "mtcrf 0b1111111, 3",
+               "isel 4, 1, 2, 2"
+               ]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x1004
+        initial_regs[2] = 0x1008
+        initial_regs[3] = 0x00ee
+        with Program(lst, bigendian) as program:
+            self.run_tst_program(program, [3, 4])
+
+    def test_isel_2(self):
+        lst = ["addi 1, 0, 0x1004",
+               "addi 2, 0, 0x1008",
+               "addi 3, 0, 0x01ee",
+               "mtcrf 0b1111111, 3",
+               "isel 4, 1, 2, 30"
+               ]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x1004
+        initial_regs[2] = 0x1008
+        initial_regs[3] = 0x00ee
+        with Program(lst, bigendian) as program:
+            self.run_tst_program(program, [3, 4])
+
     @unittest.skip("disable")
     def test_2_load_store(self):
         lst = ["addi 1, 0, 0x1004",
@@ -330,7 +359,7 @@ class GeneralTestCases(FHDLTestCase):
         with Program(lst, bigendian) as program:
             self.run_tst_program(program, [12])
 
-    #@unittest.skip("disable")
+    @unittest.skip("disable")
     def test_31_addis(self):
         """tests for zero not in register zero
         """