convert mul test to use Power Decode subset

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index b4c7f1fef7bf2dcae725967ab021ce3b1db7c6f9..3c7689f0cf6b6b16ca2dae332150831087b326b1 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -462,9 +462,10 @@ class ISACaller:
             self.spr['XER'][XER_bits['CA32']] = cy32
 
     def handle_overflow(self, inputs, outputs, div_overflow):
             self.spr['XER'][XER_bits['CA32']] = cy32
 
     def handle_overflow(self, inputs, outputs, div_overflow):

-        inv_a = yield self.dec2.e.do.invert_in
-        if inv_a:
-            inputs[0] = ~inputs[0]
+        if hasattr(self.dec2.e.do, "invert_in"):
+            inv_a = yield self.dec2.e.do.invert_in
+            if inv_a:
+                inputs[0] = ~inputs[0]

 
         imm_ok = yield self.dec2.e.do.imm_data.ok
         if imm_ok:
 
         imm_ok = yield self.dec2.e.do.imm_data.ok
         if imm_ok:

diff --git a/src/soc/fu/mul/test/test_pipe_caller.py b/src/soc/fu/mul/test/test_pipe_caller.py
index d45f19787fd3af5548ab8a466e9ecdb2137d3877..1c2ad912e3e7904a5bb9f42591a2cf1607915e6a 100644 (file)
--- a/src/soc/fu/mul/test/test_pipe_caller.py
+++ b/src/soc/fu/mul/test/test_pipe_caller.py
@@ -189,9 +189,11 @@ class TestRunner(unittest.TestCase):
         comb = m.d.comb
         instruction = Signal(32)
 
         comb = m.d.comb
         instruction = Signal(32)
 

-        pdecode = create_pdecode()
+        fn_name = "MUL"
+        opkls = MulPipeSpec.opsubsetkls

 
 

-        m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
+        m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name)
+        pdecode = pdecode2.dec

 
         pspec = MulPipeSpec(id_wid=2)
         m.submodules.alu = alu = MulBasePipe(pspec)
 
         pspec = MulPipeSpec(id_wid=2)
         m.submodules.alu = alu = MulBasePipe(pspec)


@@ -261,7 +263,7 @@ class TestRunner(unittest.TestCase):
 
     def check_alu_outputs(self, alu, dec2, sim, code):
 
 
     def check_alu_outputs(self, alu, dec2, sim, code):
 

-        rc = yield dec2.e.do.rc.data
+        rc = yield dec2.e.do.rc.rc

         cridx_ok = yield dec2.e.write_cr.ok
         cridx = yield dec2.e.write_cr.data
 
         cridx_ok = yield dec2.e.write_cr.ok
         cridx = yield dec2.e.write_cr.data