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remove unneeded imports
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 6 Jun 2020 04:43:06 +0000
(
05:43
+0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 6 Jun 2020 04:43:06 +0000
(
05:43
+0100)
src/soc/fu/alu/pipe_data.py
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src/soc/fu/branch/pipe_data.py
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src/soc/fu/cr/pipe_data.py
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src/soc/fu/ldst/pipe_data.py
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src/soc/fu/logical/pipe_data.py
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src/soc/fu/shift_rot/pipe_data.py
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src/soc/fu/spr/pipe_data.py
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src/soc/fu/trap/pipe_data.py
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diff --git
a/src/soc/fu/alu/pipe_data.py
b/src/soc/fu/alu/pipe_data.py
index 4039096ab4d6c8b7b4d9f247b1011d5c64a47a3d..71363049ba5a437a708e53dfbc3370f17aa394d1 100644
(file)
--- a/
src/soc/fu/alu/pipe_data.py
+++ b/
src/soc/fu/alu/pipe_data.py
@@
-1,8
+1,5
@@
-from nmigen import Signal, Const, Cat
from soc.fu.alu.alu_input_record import CompALUOpSubset
from soc.fu.pipe_data import IntegerData, CommonPipeSpec
from soc.fu.alu.alu_input_record import CompALUOpSubset
from soc.fu.pipe_data import IntegerData, CommonPipeSpec
-from ieee754.fpcommon.getop import FPPipeContext
-from soc.decoder.power_decoder2 import Data
class ALUInputData(IntegerData):
class ALUInputData(IntegerData):
diff --git
a/src/soc/fu/branch/pipe_data.py
b/src/soc/fu/branch/pipe_data.py
index 74edaa1f75e21a39ad9a680e79e879d97ac8493a..1ebfc05bfbdab5ed85b0a6a91b455562fb8b9d57 100644
(file)
--- a/
src/soc/fu/branch/pipe_data.py
+++ b/
src/soc/fu/branch/pipe_data.py
@@
-23,9
+23,6
@@
op_bctarl CR, TAR, CTR
"""
op_bctarl CR, TAR, CTR
"""
-from nmigen import Signal, Const, Cat
-from ieee754.fpcommon.getop import FPPipeContext
-from soc.decoder.power_decoder2 import Data
from soc.fu.pipe_data import IntegerData, CommonPipeSpec
from soc.fu.branch.br_input_record import CompBROpSubset # TODO: replace
from soc.fu.pipe_data import IntegerData, CommonPipeSpec
from soc.fu.branch.br_input_record import CompBROpSubset # TODO: replace
diff --git
a/src/soc/fu/cr/pipe_data.py
b/src/soc/fu/cr/pipe_data.py
index 00f24dbdf51c299ce806c807ce434521750fe6ee..06c7bfb7e8d209b4ed5570e35f71778b9c859901 100644
(file)
--- a/
src/soc/fu/cr/pipe_data.py
+++ b/
src/soc/fu/cr/pipe_data.py
@@
-2,11
+2,8
@@
Links:
* https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
"""
Links:
* https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
"""
-from nmigen import Signal, Const, Cat
-from ieee754.fpcommon.getop import FPPipeContext
from soc.fu.pipe_data import IntegerData, CommonPipeSpec
from soc.fu.cr.cr_input_record import CompCROpSubset
from soc.fu.pipe_data import IntegerData, CommonPipeSpec
from soc.fu.cr.cr_input_record import CompCROpSubset
-from soc.decoder.power_decoder2 import Data
class CRInputData(IntegerData):
class CRInputData(IntegerData):
diff --git
a/src/soc/fu/ldst/pipe_data.py
b/src/soc/fu/ldst/pipe_data.py
index 063bb5b1dff0bd0f1938bd0dafa023cef2e33777..b710a31f240f221fce2678276cf5bf947f91d540 100644
(file)
--- a/
src/soc/fu/ldst/pipe_data.py
+++ b/
src/soc/fu/ldst/pipe_data.py
@@
-1,8
+1,5
@@
-from nmigen import Signal, Const
from soc.fu.alu.alu_input_record import CompLDSTOpSubset
from soc.fu.alu.alu_input_record import CompLDSTOpSubset
-from soc.fu.pipe_data import IntegerData, CommonPipeSpec
-from ieee754.fpcommon.getop import FPPipeContext
-from soc.decoder.power_decoder2 import Data
+from soc.fu.pipe_data import IntegerData
class LDSTInputData(IntegerData):
class LDSTInputData(IntegerData):
diff --git
a/src/soc/fu/logical/pipe_data.py
b/src/soc/fu/logical/pipe_data.py
index 16cd3f5cae74ca683b3d1a26a43aa28cce09934e..82092b4707bdbda1ca8a7f8bc865b0fb863400ce 100644
(file)
--- a/
src/soc/fu/logical/pipe_data.py
+++ b/
src/soc/fu/logical/pipe_data.py
@@
-1,7
+1,4
@@
-from nmigen import Signal, Const, Cat
-from ieee754.fpcommon.getop import FPPipeContext
from soc.fu.pipe_data import IntegerData
from soc.fu.pipe_data import IntegerData
-from soc.decoder.power_decoder2 import Data
from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec
from soc.fu.logical.logical_input_record import CompLogicalOpSubset
from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec
from soc.fu.logical.logical_input_record import CompLogicalOpSubset
diff --git
a/src/soc/fu/shift_rot/pipe_data.py
b/src/soc/fu/shift_rot/pipe_data.py
index 16f0655435a75eab03fbe5dfb543a143b51ad8fc..280a757566bd58acd2fc50e97a170a0165dc528b 100644
(file)
--- a/
src/soc/fu/shift_rot/pipe_data.py
+++ b/
src/soc/fu/shift_rot/pipe_data.py
@@
-1,10
+1,6
@@
-from nmigen import Signal, Const, Cat
-from nmutil.dynamicpipe import SimpleHandshakeRedir
from soc.fu.shift_rot.sr_input_record import CompSROpSubset
from soc.fu.shift_rot.sr_input_record import CompSROpSubset
-from ieee754.fpcommon.getop import FPPipeContext
from soc.fu.pipe_data import IntegerData, CommonPipeSpec
from soc.fu.logical.pipe_data import LogicalOutputData
from soc.fu.pipe_data import IntegerData, CommonPipeSpec
from soc.fu.logical.pipe_data import LogicalOutputData
-from nmutil.dynamicpipe import SimpleHandshakeRedir
class ShiftRotInputData(IntegerData):
class ShiftRotInputData(IntegerData):
diff --git
a/src/soc/fu/spr/pipe_data.py
b/src/soc/fu/spr/pipe_data.py
index 007610af42901ee58732ce76dfe30e54af413df8..48439200b33e1170a8840c19e646e222010dd845 100644
(file)
--- a/
src/soc/fu/spr/pipe_data.py
+++ b/
src/soc/fu/spr/pipe_data.py
@@
-9,10
+9,7
@@
Links:
* https://libre-soc.org/openpower/isa/sprset/
"""
* https://libre-soc.org/openpower/isa/sprset/
"""
-from nmigen import Signal, Const
-from ieee754.fpcommon.getop import FPPipeContext
from soc.fu.pipe_data import IntegerData
from soc.fu.pipe_data import IntegerData
-from soc.decoder.power_decoder2 import Data
from soc.fu.spr.spr_input_record import CompSPROpSubset
from soc.fu.spr.spr_input_record import CompSPROpSubset
@@
-43,9
+40,3
@@
class SPROutputData(IntegerData):
class SPRPipeSpec:
regspec = (SPRInputData.regspec, SPROutputData.regspec)
opsubsetkls = CompSPROpSubset
class SPRPipeSpec:
regspec = (SPRInputData.regspec, SPROutputData.regspec)
opsubsetkls = CompSPROpSubset
- def __init__(self, id_wid, op_wid):
- self.id_wid = id_wid
- self.op_wid = op_wid
- self.opkls = lambda _: self.opsubsetkls(name="op")
- self.stage = None
- self.pipekls = SimpleHandshakeRedir
diff --git
a/src/soc/fu/trap/pipe_data.py
b/src/soc/fu/trap/pipe_data.py
index e0cc881ecdcf076359cc094afae91f08f5aac52c..6819fb4f065d585c5d5a1b0902decaff83ba2b07 100644
(file)
--- a/
src/soc/fu/trap/pipe_data.py
+++ b/
src/soc/fu/trap/pipe_data.py
@@
-1,8
+1,4
@@
-from nmigen import Signal, Const
-from ieee754.fpcommon.getop import FPPipeContext
from soc.fu.pipe_data import IntegerData
from soc.fu.pipe_data import IntegerData
-from soc.decoder.power_decoder2 import Data
-from nmutil.dynamicpipe import SimpleHandshakeRedir
from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
@@
-35,9
+31,3
@@
class TrapOutputData(IntegerData):
class TrapPipeSpec:
regspec = (TrapInputData.regspec, TrapOutputData.regspec)
opsubsetkls = CompALUOpSubset
class TrapPipeSpec:
regspec = (TrapInputData.regspec, TrapOutputData.regspec)
opsubsetkls = CompALUOpSubset
- def __init__(self, id_wid, op_wid):
- self.id_wid = id_wid
- self.op_wid = op_wid
- self.opkls = lambda _: self.opsubsetkls(name="op")
- self.stage = None
- self.pipekls = SimpleHandshakeRedir