projects
/
soc.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
|
inline
| side by side (parent:
105e2a3
)
Disable data value output on NOP
author
Cesar Strauss
<cestrauss@gmail.com>
Fri, 1 Jan 2021 12:59:49 +0000
(09:59 -0300)
committer
Cesar Strauss
<cestrauss@gmail.com>
Fri, 1 Jan 2021 12:59:49 +0000
(09:59 -0300)
src/soc/experiment/alu_hier.py
patch
|
blob
|
history
diff --git
a/src/soc/experiment/alu_hier.py
b/src/soc/experiment/alu_hier.py
index c01cc26ee2d5eb94811cfdd82a47f2f03c04c2a0..39e9cb92851652f3e39063285e60b67eac2344ae 100644
(file)
--- a/
src/soc/experiment/alu_hier.py
+++ b/
src/soc/experiment/alu_hier.py
@@
-317,11
+317,13
@@
class ALU(Elaboratable):
# choose between zero-delay output, or registered
with m.If(go_now):
# choose between zero-delay output, or registered
with m.If(go_now):
- m.d.comb += self.o.data.eq(sub.o)
+ with m.If(self.o.ok):
+ m.d.comb += self.o.data.eq(sub.o)
m.d.comb += self.cr.ok.eq(self.op.rc.rc)
# only present the result at the last computation cycle
with m.Elif(alu_done):
m.d.comb += self.cr.ok.eq(self.op.rc.rc)
# only present the result at the last computation cycle
with m.Elif(alu_done):
- m.d.comb += self.o.data.eq(alu_r)
+ with m.If(self.o.ok):
+ m.d.comb += self.o.data.eq(alu_r)
m.d.comb += self.cr.ok.eq(cr_ok_r)
# determine condition register bits based on the data output value
m.d.comb += self.cr.ok.eq(cr_ok_r)
# determine condition register bits based on the data output value