Migrate imports to use absolute imports

diff --git a/src/soc/decoder/power_decoder.py b/src/soc/decoder/power_decoder.py
index 5b5e710393f3b504bc52a4d992431340714648fa..eb7c80a65f5d1ea9d6d1580b0bb699c315b2cfa9 100644 (file)
--- a/src/soc/decoder/power_decoder.py
+++ b/src/soc/decoder/power_decoder.py
@@ -55,12 +55,13 @@ Top Level:
 
 from nmigen import Module, Elaboratable, Signal
 from nmigen.cli import rtlil
-from power_enums import (Function, Form, InternalOp, In1Sel, In2Sel, In3Sel,
-                         OutSel, RC, LdstLen, CryIn, get_csv, single_bit_flags,
+from soc.decoder.power_enums import (Function, Form, InternalOp,
+                         In1Sel, In2Sel, In3Sel, OutSel, RC, LdstLen,
+                         CryIn, get_csv, single_bit_flags,
                          get_signal_name, default_values)
 from collections import namedtuple
-from power_fields import DecodeFields
-from power_fieldsn import SigDecode, SignalBitRange
+from soc.decoder.power_fields import DecodeFields
+from soc.decoder.power_fieldsn import SigDecode, SignalBitRange
 
 Subdecoder = namedtuple("Subdecoder", ["pattern", "opcodes", "opint",
                                        "bitsel", "suffix", "subdecoders"])

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 1b7435a0eee992d5d5b52a68149676f49f431633..81805a7355d582a506981b2d49879d7fbf1843c4 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -6,9 +6,10 @@ based on Anton Blanchard microwatt decode2.vhdl
 from nmigen import Module, Elaboratable, Signal, Mux, Const
 from nmigen.cli import rtlil
 
-from power_decoder import create_pdecode
-from power_enums import (InternalOp, CryIn, Function, LdstLen,
-                         In1Sel, In2Sel, In3Sel, OutSel, SPR, RC)
+from soc.decoder.power_decoder import create_pdecode
+from soc.decoder.power_enums import (InternalOp, CryIn, Function,
+                                     LdstLen, In1Sel, In2Sel, In3Sel,
+                                     OutSel, SPR, RC)
 
 
 class DecodeA(Elaboratable):

diff --git a/src/soc/decoder/power_fields.py b/src/soc/decoder/power_fields.py
index a6352206056d14cbc4f018c32ae4ebb579345812..aabf591af34a0eee7a6aa697fd89b6ffe998dcb5 100644 (file)
--- a/src/soc/decoder/power_fields.py
+++ b/src/soc/decoder/power_fields.py
@@ -1,5 +1,5 @@
 from collections import OrderedDict, namedtuple
-from power_enums import download_wiki_file
+from soc.decoder.power_enums import download_wiki_file
 
 
 class BitRange(OrderedDict):

diff --git a/src/soc/decoder/power_fieldsn.py b/src/soc/decoder/power_fieldsn.py
index e603bbd3a68dca45e8c42cf1dac80a5b24034a4d..a5e03a114ec54d915deb13f20c99e8ab59078dc5 100644 (file)
--- a/src/soc/decoder/power_fieldsn.py
+++ b/src/soc/decoder/power_fieldsn.py
@@ -1,5 +1,5 @@
 from collections import OrderedDict
-from power_fields import DecodeFields, BitRange
+from soc.decoder.power_fields import DecodeFields, BitRange
 from nmigen import Module, Elaboratable, Signal, Cat
 from nmigen.cli import rtlil