add stub regfiles.py

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
new file mode 100644 (file)
index 0000000..b848ea4
--- /dev/null
+++ b/src/soc/regfile/regfiles.py
@@ -0,0 +1,19 @@
+# POWER9 Register Files
+"""POWER9 regfiles
+
+Defines the following register files:
+
+    * INT regfile
+    * SPR regfile
+    * CR regfile
+    * XER regfile
+    * FAST regfile
+
+Links:
+
+* https://bugs.libre-soc.org/show_bug.cgi?id=345
+* https://libre-soc.org/3d_gpu/architecture/regfile/
+* https://libre-soc.org/openpower/isatables/sprs.csv
+"""
+
+# TODO