move reg setup to earlier in test

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 6a3f5cb2df02a11ed348e641fd596aa3b13f90fe..877c215ebb5cb6aa55a3acfcd88e83a8ccb22326 100644 (file)
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -137,6 +137,10 @@ class TestRunner(FHDLTestCase):
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))
 
+                # set up INT regfile, "direct" write from sim data
+                for i in range(32):
+                    yield core.regs.int.regs[i].reg.eq(test.regs[i])
+
                 index = sim.pc.CIA.value//4
                 while index < len(instructions):
                     ins, code = instructions[index]
@@ -157,10 +161,6 @@ class TestRunner(FHDLTestCase):
                     yield from set_issue(core, pdecode2, sim)
                     yield Settle()
 
-                    # set up INT regfile, "direct" write from sim data
-                    for i in range(32):
-                        yield core.regs.int.regs[i].reg.eq(test.regs[i])
-
                     yield from wait_for_busy_clear(core)
                     yield core.ivalid_i.eq(0)