Add copyright to files in fu/ that I was the primary author on

diff --git a/src/soc/fu/alu/main_stage.py b/src/soc/fu/alu/main_stage.py
index b2d2279cf80dec3670d70e5b65359c92a9794acf..16950629c743a301c62b7712420aeb436cce0e76 100644 (file)
--- a/src/soc/fu/alu/main_stage.py
+++ b/src/soc/fu/alu/main_stage.py
@@ -3,6 +3,8 @@
 # as well as carry and overflow generation. This module
 # however should not gate the carry or overflow, that's up to the
 # output stage
+
+# Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const)
 from nmutil.pipemodbase import PipeModBase
 from nmutil.extend import exts

diff --git a/src/soc/fu/branch/main_stage.py b/src/soc/fu/branch/main_stage.py
index 39631afdca281c1b280765281cbae5cb000b35b3..8a1b5f0ba0069063671c9bd7c7f23b683c56bab7 100644 (file)
--- a/src/soc/fu/branch/main_stage.py
+++ b/src/soc/fu/branch/main_stage.py
@@ -23,6 +23,7 @@ Links:
 * https://bugs.libre-soc.org/show_bug.cgi?id=335
 * https://libre-soc.org/openpower/isa/branch/
 """
+# Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
 
 from nmigen import (Module, Signal, Cat, Mux, Const, Array)
 from nmutil.pipemodbase import PipeModBase

diff --git a/src/soc/fu/cr/main_stage.py b/src/soc/fu/cr/main_stage.py
index 27aa667042c2891d3f3de8e43290cdb2d332c53a..36f587eb0b42b28e4f7dca3db765c64f21c31469 100644 (file)
--- a/src/soc/fu/cr/main_stage.py
+++ b/src/soc/fu/cr/main_stage.py
@@ -8,6 +8,7 @@
 # own "Register File" (indexed by bt, ba and bb),
 # exactly how INT regs are done (by RA, RB, RS and RT)
 # however we are pushed for time so do it as *one* register.
+# Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
 
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
 from nmutil.pipemodbase import PipeModBase

diff --git a/src/soc/fu/logical/main_stage.py b/src/soc/fu/logical/main_stage.py
index ea102358332a6bf565d1b3bf195a5d2ad4b9fd2b..d6ae4a2f9e4dc0c33c95183c438190443fc69973 100644 (file)
--- a/src/soc/fu/logical/main_stage.py
+++ b/src/soc/fu/logical/main_stage.py
@@ -5,6 +5,7 @@
 # This module however should not gate the carry or overflow, that's up
 # to the output stage
 
+# Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
 from nmutil.pipemodbase import PipeModBase
 from nmutil.clz import CLZ

diff --git a/src/soc/fu/shift_rot/main_stage.py b/src/soc/fu/shift_rot/main_stage.py
index 0ab4c460da359276273b452f355d3ebcfcbf2a38..7d9dad09cb53362668fce85b43a43dc5c0c7c0fe 100644 (file)
--- a/src/soc/fu/shift_rot/main_stage.py
+++ b/src/soc/fu/shift_rot/main_stage.py
@@ -2,6 +2,7 @@
 # instructions, as well as carry and overflow generation. This module
 # however should not gate the carry or overflow, that's up to the
 # output stage
+# Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const)
 from nmutil.pipemodbase import PipeModBase
 from soc.fu.logical.pipe_data import LogicalOutputData

diff --git a/src/soc/fu/shift_rot/maskgen.py b/src/soc/fu/shift_rot/maskgen.py
index 89246e0b17fb3db9fd9c476e3c61af95b8d7b7a5..03072110e702a48d8573f321010d934c00e9b3b0 100644 (file)
--- a/src/soc/fu/shift_rot/maskgen.py
+++ b/src/soc/fu/shift_rot/maskgen.py
@@ -1,5 +1,6 @@
 from nmigen import (Elaboratable, Signal, Module)
 import math
+# Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
 
 class MaskGen(Elaboratable):
     """MaskGen - create a diff mask