correct comments

diff --git a/src/soc/decoder/isa/test_caller_svp64_predication.py b/src/soc/decoder/isa/test_caller_svp64_predication.py
index afd50141373f73de9351dcfe57e69edf8cd29bad..d962c0db1a708d88a43225b29aced25e8b47ba0b 100644 (file)
--- a/src/soc/decoder/isa/test_caller_svp64_predication.py
+++ b/src/soc/decoder/isa/test_caller_svp64_predication.py
@@ -53,7 +53,7 @@ class DecoderTestCase(FHDLTestCase):
         # therefore the operation that's carried out is:
         #       GPR(10) = extsb(GPR(5))
         #
-        # this is a type of back-to-back VGATHER and VSCATTER but it applies
+        # this is a type of back-to-back VREDUCE and VEXPAND but it applies
         # to *operations*, not just MVs like in traditional Vector ISAs
         # ascii graphic:
         #