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add --disable-svp64 to litex sim build
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 24 Mar 2021 09:26:36 +0000 (09:26 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 24 Mar 2021 09:26:40 +0000 (09:26 +0000)
Makefile patch | blob | history

diff --git a/Makefile b/Makefile
index 0ab0037e775e143df33b60909638db64534c995f..20fe492187474443575dfca71efe2fe25a01b2b1 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -24,7 +24,7 @@ develop:
        python3 src/soc/decoder/pseudo/pywriter.py
 
 run_sim: install
-       python3 src/soc/simple/issuer_verilog.py \
+       python3 src/soc/simple/issuer_verilog.py --disable-svp64\
                        src/soc/litex/florent/libresoc/libresoc.v
        python3 src/soc/litex/florent/sim.py --cpu=libresoc