add missing MSRSpec import

diff --git a/src/soc/experiment/test/test_ldst_pi.py b/src/soc/experiment/test/test_ldst_pi.py
index fa7bc660607b1cceec6a43298923bf1f4105ddf3..003edf1264566ac27528a55df97b88030f976d38 100644 (file)
--- a/src/soc/experiment/test/test_ldst_pi.py
+++ b/src/soc/experiment/test/test_ldst_pi.py
@@ -27,6 +27,8 @@ from soc.fu.ldst.loadstore import LoadStore1
 from soc.experiment.mmu import MMU
 
 from nmigen.compat.sim import run_simulation
+from openpower.decoder.power_enums import MSRSpec
+
 
 msr_default = MSRSpec(pr=1, dr=0, sf=1) # 64 bit by default