argh issue with yosys ABC
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 3 Dec 2020 15:51:56 +0000 (15:51 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 3 Dec 2020 15:51:56 +0000 (15:51 +0000)
src/soc/litex/florent/ls180soc.py

index 8566988ac1326f19c7d4ca67735bc55e5cc00e45..f8c71ebbbaf55bf685ed18639a1cb8bfcf66f280 100755 (executable)
@@ -339,7 +339,8 @@ class LibreSoCSim(SoCCore):
             sdram_module          = sdram_module,
             sdram_data_width      = sdram_data_width,
             integrated_rom_size      = 0, # if ram_fname else 0x10000,
             sdram_module          = sdram_module,
             sdram_data_width      = sdram_data_width,
             integrated_rom_size      = 0, # if ram_fname else 0x10000,
-            integrated_sram_size     = 0x1000,
+            #integrated_sram_size     = 0x1000, - problem with yosys ABC
+            integrated_sram_size     = 0x200,
             #integrated_main_ram_init  = ram_init,
             integrated_main_ram_size = 0x00000000 if with_sdram \
                                         else 0x10000000 , # 256MB
             #integrated_main_ram_init  = ram_init,
             integrated_main_ram_size = 0x00000000 if with_sdram \
                                         else 0x10000000 , # 256MB