Disallow unknown encmodes in SVP64 Assembly

diff --git a/src/soc/sv/trans/svp64.py b/src/soc/sv/trans/svp64.py
index 6bdfb98a1ee41b1b92b6b5239bac55033df6227f..5df66ce1678b70e088a8492c489fd7b353507d51 100644 (file)
--- a/src/soc/sv/trans/svp64.py
+++ b/src/soc/sv/trans/svp64.py
@@ -482,6 +482,8 @@ class SVP64Asm:
                     mapreduce_crm = True
                 elif encmode == 'svm': # sub-vector mode
                     mapreduce_svm = True
+                else:
+                    raise AssertionError("unknown encmode %s" % encmode)
 
             if ptype == '2P':
                 # since m=xx takes precedence (overrides) sm=xx and dm=xx,