argh! frickin MACos terminal expanded out to 86x30 not 80x30

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index 5f76ae6fc160160c3e066534f0c673ddf4b90133..762ed582890a8fcc9d6d35c63dc036e6f9bd71f4 100644 (file)
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -153,11 +153,12 @@ class DataMerger(Elaboratable):
     then uses that row, based on matching address bits, to merge (OR) all data
     rows into the output.
 
-    Basically, by the time DataMerger is used, all of its incoming data is determined
-    not to conflict.  The last step before actually submitting the request to the
-    Memory Subsystem is to work out which requests, on the same 128-bit cache line,
-    can be "merged" due to them being: (A) on the same address (bits 4 and above)
-    (B) having byte-enable lines that (as previously mentioned) do not conflict.
+    Basically, by the time DataMerger is used, all of its incoming data is
+    determined not to conflict.  The last step before actually submitting
+    the request to the Memory Subsystem is to work out which requests,
+    on the same 128-bit cache line, can be "merged" due to them being:
+    (A) on the same address (bits 4 and above) (B) having byte-enable
+    lines that (as previously mentioned) do not conflict.
 
     Therefore, put simply, this module will:
     (1) pick a row (any row) and identify it by an index labelled "idx"