Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

diff --git a/libreriscv b/libreriscv
index 12e9237b896ad233cb18946b34dab17d976f415c..d83e5ccbacd56e762bedc660cdd930264e12b81b 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 12e9237b896ad233cb18946b34dab17d976f415c
+Subproject commit d83e5ccbacd56e762bedc660cdd930264e12b81b

diff --git a/src/soc/fu/spr/formal/proof_main_stage.py b/src/soc/fu/spr/formal/proof_main_stage.py
index 11ff8d8e6602481083ccdb61832d3232f3670c02..2c7121152deb263ec87828803ebe5dbc876713f5 100644 (file)
--- a/src/soc/fu/spr/formal/proof_main_stage.py
+++ b/src/soc/fu/spr/formal/proof_main_stage.py
@@ -23,7 +23,7 @@ from soc.decoder.power_enums import MicrOp, SPR, XER_bits
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange
 
-
+# use POWER numbering. sigh.
 def xer_bit(name):
     return 63-XER_bits[name]
 

diff --git a/src/soc/minerva/units/fetch.py b/src/soc/minerva/units/fetch.py
index b7cdad11bf3528c848f2a10ce62918f6933fec5c..04e1f58d51664dad25a8e74ad1e4c4638c922e29 100644 (file)
--- a/src/soc/minerva/units/fetch.py
+++ b/src/soc/minerva/units/fetch.py
@@ -178,7 +178,7 @@ class CachedFetchUnit(FetchUnitInterface, Elaboratable):
             ]
         with m.Elif(f_icache_select):
             m.d.comb += [
-                self.f_busy_o.eq(icache.s2_re & icache.s2_miss),
+                self.f_busy_o.eq(icache.s2_miss),
                 self.f_instr_o.eq(icache.s2_rdata)
             ]
         with m.Else():

diff --git a/src/soc/minerva/units/loadstore.py b/src/soc/minerva/units/loadstore.py
index f3ca09d7af248f5d1826e93529b783dd9ffc39cf..499daf216857f601e983bad8ca1b5242bcdddde8 100644 (file)
--- a/src/soc/minerva/units/loadstore.py
+++ b/src/soc/minerva/units/loadstore.py
@@ -184,22 +184,21 @@ class CachedLoadStoreUnit(LoadStoreUnitInterface, Elaboratable):
         m.d.comb += dba.bus.connect(self.dbus)
 
         wrbuf_port = dbus_arbiter.port(priority=0)
-        with m.If(wrbuf_port.cyc):
+        m.d.comb += [
+            wrbuf_port.cyc.eq(wrbuf.r_rdy),
+            wrbuf_port.we.eq(Const(1)),
+        ]
+        with m.If(wrbuf_port.stb):
             with m.If(wrbuf_port.ack | wrbuf_port.err):
-                m.d.sync += [
-                    wrbuf_port.cyc.eq(0),
-                    wrbuf_port.stb.eq(0)
-                ]
+                m.d.sync += wrbuf_port.stb.eq(0)
                 m.d.comb += wrbuf.r_en.eq(1)
         with m.Elif(wrbuf.r_rdy):
             m.d.sync += [
-                wrbuf_port.cyc.eq(1),
                 wrbuf_port.stb.eq(1),
                 wrbuf_port.adr.eq(wrbuf_r_data.addr),
                 wrbuf_port.sel.eq(wrbuf_r_data.mask),
                 wrbuf_port.dat_w.eq(wrbuf_r_data.data)
             ]
-        m.d.comb += wrbuf_port.we.eq(Const(1))
 
         dcache_port = dba.port(priority=1)
         cti = Mux(dcache.bus_last, Cycle.END, Cycle.INCREMENT)
@@ -258,9 +257,9 @@ class CachedLoadStoreUnit(LoadStoreUnitInterface, Elaboratable):
                 self.m_busy_o.eq(0),
                 self.m_ld_data_o.eq(0)
             ]
-        with m.Elif(m_dcache_select):
+        with m.Elif(self.m_load & m_dcache_select):
             m.d.comb += [
-                self.m_busy_o.eq(dcache.s2_re & dcache.s2_miss),
+                self.m_busy_o.eq(dcache.s2_miss),
                 self.m_ld_data_o.eq(dcache.s2_rdata)
             ]
         with m.Else():