split out ilang tests

diff --git a/src/soc/fu/div/test/runner.py b/src/soc/fu/div/test/runner.py
index ee4d842d0c0dd2a83952294ac0a5d2a25d10eaaf..ff2a1385d122303476aefa7ba1df1a113bdae928 100644 (file)
--- a/src/soc/fu/div/test/runner.py
+++ b/src/soc/fu/div/test/runner.py
@@ -106,16 +106,6 @@ class DivRunner(unittest.TestCase):
         self.test_data = test_data
         self.div_pipe_kind = div_pipe_kind
 
-    def write_ilang(self):
-        pspec = DivPipeSpec(id_wid=2, div_pipe_kind=self.div_pipe_kind)
-        alu = DivBasePipe(pspec)
-        vl = rtlil.convert(alu, ports=alu.ports())
-        with open(f"div_pipeline_{div_pipe_kind.name}.il", "w") as f:
-            f.write(vl)
-
-    def test_write_ilang(self):
-        self.write_ilang(self.div_pipe_kind)
-
     def execute(self, alu, instruction, pdecode2, test):
         prog = test.program
         isa_sim = ISA(pdecode2, test.regs, test.sprs, test.cr,

diff --git a/src/soc/fu/div/test/test_pipe_ilang.py b/src/soc/fu/div/test/test_pipe_ilang.py
new file mode 100644 (file)
index 0000000..ce472ca
--- /dev/null
+++ b/src/soc/fu/div/test/test_pipe_ilang.py
@@ -0,0 +1,26 @@
+import unittest
+from nmigen.cli import rtlil
+from soc.fu.div.pipe_data import DivPipeSpec, DivPipeKind
+from soc.fu.div.pipeline import DivBasePipe
+
+
+class TestPipeIlang(unittest.TestCase):
+    def write_ilang(self, div_pipe_kind):
+        pspec = DivPipeSpec(id_wid=2, div_pipe_kind=div_pipe_kind)
+        alu = DivBasePipe(pspec)
+        vl = rtlil.convert(alu, ports=alu.ports())
+        with open(f"div_pipeline_{div_pipe_kind.name}.il", "w") as f:
+            f.write(vl)
+
+    def test_div_pipe_core(self):
+        self.write_ilang(DivPipeKind.DivPipeCore)
+
+    def test_div_pipe_core(self):
+        self.write_ilang(DivPipeKind.FSMDivCore)
+
+    def test_div_pipe_core(self):
+        self.write_ilang(DivPipeKind.SimOnly)
+
+
+if __name__ == "__main__":
+    unittest.main()