give module appropriate top-level name in microwatt compat mode

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 6fead5eedfa48ecc5ee225eddf839b6c1a5f6386..0ff83d691807799ae2c86d5a69fa06f6e8e1af5b 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -140,9 +140,11 @@ if __name__ == '__main__':
 
     if args.mwcompat:
         dut = TestIssuerInternal(pspec)
+        name = "external_core_top"
     else:
         dut = TestIssuer(pspec)
+        name = "test_issuer"
 
-    vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer")
+    vl = verilog.convert(dut, ports=dut.external_ports(), name=name)
     with open(args.output_filename, "w") as f:
         f.write(vl)