move TestCase to common location

diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py
index 6f6fd2d3d01872e63d7fce989265dcf96e99b752..e066ff6a9288c006a93d0f6637be4f4518c34ba1 100644 (file)
--- a/src/soc/fu/cr/test/test_pipe_caller.py
+++ b/src/soc/fu/cr/test/test_pipe_caller.py
@@ -12,19 +12,12 @@ from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
 
 
+from soc.fu.test.common import TestCase
 from soc.fu.cr.pipeline import CRBasePipe
 from soc.fu.cr.pipe_data import CRPipeSpec
 import random
 
 
-class TestCase:
-    def __init__(self, program, regs, sprs, cr, name):
-        self.program = program
-        self.regs = regs
-        self.sprs = sprs
-        self.name = name
-        self.cr = cr
-
 
 # This test bench is a bit different than is usual. Initially when I
 # was writing it, I had all of the tests call a function to create a
@@ -52,10 +45,10 @@ class CRTestCase(FHDLTestCase):
         super().__init__(name)
         self.test_name = name
 
-    def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={},
+    def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
                         initial_cr=0):
-        tc = TestCase(prog, initial_regs, initial_sprs, initial_cr,
-                      self.test_name)
+        tc = TestCase(prog, self.test_name,
+                      regs=initial_regs, sprs=initial_sprs, cr=initial_cr)
         test_data.append(tc)
 
     def test_crop(self):

diff --git a/src/soc/fu/test/__init__.py b/src/soc/fu/test/__init__.py
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
new file mode 100644 (file)
index 0000000..bd8a35a
--- /dev/null
+++ b/src/soc/fu/test/common.py
@@ -0,0 +1,13 @@
+class TestCase:
+    def __init__(self, program, name, regs=None, sprs=None, cr=0):
+        self.program = program
+        self.name = name
+
+        if regs is None:
+            regs = [0] * 32
+        if sprs is None:
+            sprs = {}
+        self.regs = regs
+        self.sprs = sprs
+        self.cr = cr
+