add way to bypass PLL for ECP5 and sim

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index aafae394e101cb4d9ab9aff0080a0b6e896cf36e..64350c96ab1bc7a93ee089a4c68dd28afcc457b3 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -447,15 +447,23 @@ class TestIssuerInternal(Elaboratable):
 class TestIssuer(Elaboratable):
     def __init__(self, pspec):
         self.ti = TestIssuerInternal(pspec)
+
         self.pll = DummyPLL()
         self.clksel = ClockSelect()
 
+        # PLL direct clock or not
+        self.pll_en = hasattr(pspec, "use_pll") and pspec.pll_en
+
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb
 
-        # TestIssuer runs at internal clock rate
-        m.submodules.ti = ti = DomainRenamer("intclk")(self.ti)
+        if self.pll_en:
+            # TestIssuer runs at internal clock rate
+            m.submodules.ti = ti = DomainRenamer("intclk")(self.ti)
+        else:
+            # TestIssuer runs at direct clock
+            m.submodules.ti = ti = self.ti
         # ClockSelect runs at PLL output internal clock rate
         m.submodules.clksel = clksel = DomainRenamer("pllclk")(self.clksel)
         m.submodules.pll = pll = self.pll

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 383afa0d6e8d627b2fdb99f0327d11243fc62faa..95eb748d1573c3d37c7f07c6003f222a263380b7 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -29,6 +29,7 @@ if __name__ == '__main__':
                          #wb_data_wid=32,
                          xics=True,
                          #nocore=True, # to help test coriolis2 ioring
+                         use_pll=False, # bypass PLL
                          gpio=True, # for test purposes
                          debug="jtag", # set to jtag or dmi
                          units=units)