Enable read port for non-transparent memories

For some reason, the reset value (=1) of the port enable is not recognized
by the formal engine, even if the simulation is fine with it.

diff --git a/src/soc/regfile/sram_wrapper.py b/src/soc/regfile/sram_wrapper.py
index 297a935f6707036344c0504607a8791089cc964a..cba1ec21d2bc63ab7cde87aec9c4838915955409 100644 (file)
--- a/src/soc/regfile/sram_wrapper.py
+++ b/src/soc/regfile/sram_wrapper.py
@@ -599,6 +599,10 @@ class DualPortRegfile(Elaboratable):
         lvt_mem = Memory(width=self.we_width, depth=depth)
         lvt_wr = lvt_mem.write_port(granularity=1)
         lvt_rd = lvt_mem.read_port(transparent=self.transparent)
+        if not self.transparent:
+            # for some reason, formal proofs don't recognize the default
+            # reset value for this signal
+            m.d.comb += lvt_rd.en.eq(1)
         m.submodules.lvt_wr = lvt_wr
         m.submodules.lvt_rd = lvt_rd
         # generate and wire the phases for the phased memories