+ style = {
+ 'in': {'color': 'orange'},
+ 'out': {'color': 'yellow'},
+ }
+ traces = [
+ 'clk',
+ ('operation port', {'color': 'red'}, [
+ 'cu_issue_i', 'cu_busy_o',
+ {'comment': 'operation'},
+ ('oper_i_None__insn_type', {'display': 'insn_type'})]),
+ ('operand 1 port', 'in', [
+ ('cu_rd__rel_o[2:0]', {'bit': 2}),
+ ('cu_rd__go_i[2:0]', {'bit': 2}),
+ 'src1_i[15:0]']),
+ ('operand 2 port', 'in', [
+ ('cu_rd__rel_o[2:0]', {'bit': 1}),
+ ('cu_rd__go_i[2:0]', {'bit': 1}),
+ 'src2_i[15:0]']),
+ ('operand 3 port', 'in', [
+ ('cu_rd__rel_o[2:0]', {'bit': 0}),
+ ('cu_rd__go_i[2:0]', {'bit': 0}),
+ 'src1_i[15:0]']),
+ ('result port', 'out', [
+ 'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[15:0]']),
+ ('alu', {'module': 'top.cu.alu'}, [
+ ('prev port', 'in', [
+ 'oper_i_None__insn_type', 'i1[15:0]',
+ 'valid_i', 'ready_o']),
+ ('next port', 'out', [
+ 'alu_o[15:0]', 'valid_o', 'ready_i'])])]
+
+ write_gtkw("test_compunit_regspec3.gtkw",
+ "test_compunit_regspec3.vcd",
+ traces, style,
+ clk_period=1e-6,
+ module='top.cu')
+