support 32-bit mem width setting

diff --git a/src/soc/litex/core.py b/src/soc/litex/core.py
index f1fd3d816e119fc5a778b4354e17eb0c886d7817..c37f23a8f0c4d45144783da01e6d25699f4a0efe 100644 (file)
--- a/src/soc/litex/core.py
+++ b/src/soc/litex/core.py
@@ -59,6 +59,7 @@ class LibreSOC(CPU):
         self.core_busy    = Signal()   # core is running (busy)
 
         # instruction and data bus: 64-bit, 48 bit addressing
+        # sigh self.ibus  = wishbone.Interface(data_width=32, adr_width=48)
         self.ibus         = wishbone.Interface(data_width=64, adr_width=48)
         self.dbus         = wishbone.Interface(data_width=64, adr_width=48)
 
@@ -85,7 +86,8 @@ class LibreSOC(CPU):
             o_ibus__cti   = self.ibus.cti,
             o_ibus__bte   = self.ibus.bte,
             o_ibus__we    = self.ibus.we,
-            o_ibus__adr   = Cat(Signal(3), self.ibus.adr), # 64-bit
+            #o_ibus__adr   = self.ibus.adr, # 64-bit
+            sigh o_ibus__adr   = Cat(Signal(3), self.ibus.adr), # 64-bit
             o_ibus__dat_w = self.ibus.dat_w,
             o_ibus__sel   = self.ibus.sel,
             i_ibus__ack   = self.ibus.ack,

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 17cbc4d763add8b1cdc15f79b6d817d5767a9944..14a8d53dbbb4c6c3d35ed0a0a3ca5010809f97b6 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -17,7 +17,10 @@ if __name__ == '__main__':
                          imem_ifacetype='bare_wb',
                          addr_wid=48,
                          mask_wid=8,
+                         # must leave at 64
                          reg_wid=64,
+                         # set to 32 for instruction-memory width=32
+                         imem_reg_wid=64,
                          units=units)
     dut = TestIssuer(pspec)
 

diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index a353933b475d5103fe58d1068b25f6970fc3c4f6..9efb02945dec81b5a98e6bbc7016ea50d3899cb0 100644 (file)
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -44,8 +44,25 @@ def setup_i_memory(imem, startaddr, instructions):
     for i in range(mem.depth):
         yield mem._array[i].eq(0)
     yield Settle()
-    startaddr //= 4  # instructions are 32-bit
-    mask = ((1 << 64)-1)
+    startaddr //= 4 # instructions are 32-bit
+    if mem.width == 32:
+        mask = ((1<<32)-1)
+        for ins in instructions:
+            if isinstance(ins, tuple):
+                insn, code = ins
+            else:
+                insn, code = ins, ''
+            insn = insn & 0xffffffff
+            yield mem._array[startaddr].eq(insn)
+            yield Settle()
+            if insn != 0:
+                print ("instr: %06x 0x%x %s" % (4*startaddr, insn, code))
+            startaddr += 1
+            startaddr = startaddr & mask
+        return
+
+    # 64 bit
+    mask = ((1<<64)-1)
     for ins in instructions:
         if isinstance(ins, tuple):
             insn, code = ins
@@ -84,6 +101,7 @@ class TestRunner(FHDLTestCase):
                              imem_ifacetype='test_bare_wb',
                              addr_wid=48,
                              mask_wid=8,
+                             imem_reg_wid=64,
                              reg_wid=64)
         m.submodules.issuer = issuer = TestIssuer(pspec)
         imem = issuer.imem._get_memory()