whoops syntax error. submodule update

diff --git a/libreriscv b/libreriscv
index c6fdcb27f8f0fd261d200beabf218c7fc759261e..c63a58b326a2b17d617b098261f217409c65402c 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit c6fdcb27f8f0fd261d200beabf218c7fc759261e
+Subproject commit c63a58b326a2b17d617b098261f217409c65402c

diff --git a/src/soc/decoder/power_svp64.py b/src/soc/decoder/power_svp64.py
index 8bb896afcd11664edba15c42ffd93e6980df6557..85fc39747f94538489c850de09f8c661e27c4293 100644 (file)
--- a/src/soc/decoder/power_svp64.py
+++ b/src/soc/decoder/power_svp64.py
@@ -131,9 +131,9 @@ class SVP64RM:
             # more enum-friendly Ptype names.  should have done this in
             # sv_analysis.py, oh well
             if entry['SV_Ptype'] == '1P':
-                if entry['SV_Ptype'] = 'P1'
+                entry['SV_Ptype'] = 'P1'
             if entry['SV_Ptype'] == '2P':
-                if entry['SV_Ptype'] = 'P2'
+                entry['SV_Ptype'] = 'P2'
 
         return v30b