add RADIX skeleton and unit test

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 1190831d3004564015fc16d16a3bd485fa64916d..bb69f7546a75e3ae084f6f7d625ac55de29685fa 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -75,6 +75,36 @@ def create_args(reglist, extra=None):
     return retval
 
 
     return retval
 
 

+
+# see qemu/target/ppc/mmu-radix64.c for reference
+class RADIX:
+    def __init__(self, mem, caller):
+        self.mem = mem
+        self.caller = caller
+
+    def ld(self, address, width=8, swap=True, check_in_mem=False):
+        print("RADIX: ld from addr 0x{:x} width {:d}".format(address, width))
+
+        pte = self._walk_tree()
+        # use pte to caclculate phys address
+        #mem.ld(address,width,swap,check_in_mem)
+
+    # TODO implement
+    # def st(self, addr, v, width=8, swap=True):
+    # def memassign(self, addr, sz, val):
+    def _next_level(self):
+        return True
+        ## DSISR_R_BADCONFIG
+        ## read_entry
+        ## DSISR_NOPTE
+        ## Prepare for next iteration
+
+    def _walk_tree(self):
+        # walk tree starts on prtbl
+        while True:
+            ret = self._next_level()
+            if ret: return ret
+

 class Mem:
 
     def __init__(self, row_bytes=8, initial_mem=None):
 class Mem:
 
     def __init__(self, row_bytes=8, initial_mem=None):

diff --git a/src/soc/decoder/isa/test_caller_radix.py b/src/soc/decoder/isa/test_caller_radix.py
new file mode 100644 (file)
index 0000000..5292850
--- /dev/null
+++ b/src/soc/decoder/isa/test_caller_radix.py
@@ -0,0 +1,17 @@
+from nmigen import Module, Signal
+#from nmigen.back.pysim import Simulator, Delay, Settle
+from nmutil.formaltest import FHDLTestCase
+#import unittest
+from soc.decoder.isa.caller import ISACaller
+from soc.decoder.power_decoder import (create_pdecode)
+from soc.decoder.power_decoder2 import (PowerDecode2)
+from soc.simulator.program import Program
+from soc.decoder.isa.caller import ISACaller, inject, RADIX
+from soc.decoder.selectable_int import SelectableInt
+from soc.decoder.orderedset import OrderedSet
+from soc.decoder.isa.all import ISA
+
+if __name__ == "__main__":
+    radix = RADIX(None,None) #first test to avoid syntax errors
+    radix._walk_tree()
+    print("DONE")