Fix typo.

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index e0139942bfe666f5ae191a2f84ab538fccf42013..0b0f3a3624feabdf9900502ef25b587222925280 100644 (file)
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -161,7 +161,7 @@ def check_regs(dut, sim, core, test, code):
     print("core int regs", list(map(hex, intregs)))
 
     # TODO, split this out into "sim-register-getter" function
-    intregs = []
+    simregs = []
     for i in range(32):
         simregs.append(sim.gpr[i].asint())
     print("sim int regs", list(map(hex, simregs)))