add reserve (atomic) signal to LDST data structures including PortInterface

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index 6fe1e6817b20000697a419b762bbcddee58ff045..b514e7b4ab29995a0d6aed3dfb33ca4dabaddabf 100644 (file)
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -105,6 +105,9 @@ class PortInterface(RecordObject):
         # LD/ST data length (TODO: other things may be needed)
         self.data_len = Signal(4, reset_less=True)
 
+        # atomic reservation (LR/SC - ldarx / stdcx etc.)
+        self.reserve = Signal(reset_less=True)
+
         # common signals
         self.busy_o = Signal(reset_less=True)     # do not use if busy
         self.go_die_i = Signal(reset_less=True)   # back to reset
@@ -141,6 +144,7 @@ class PortInterface(RecordObject):
                 self.is_nc.eq(inport.is_nc),
                 self.is_dcbz_i.eq(inport.is_dcbz_i),
                 self.data_len.eq(inport.data_len),
+                self.reserve.eq(inport.reserve),
                 self.go_die_i.eq(inport.go_die_i),
                 self.addr.data.eq(inport.addr.data),
                 self.addr.ok.eq(inport.addr.ok),

diff --git a/src/soc/fu/ldst/ldst_input_record.py b/src/soc/fu/ldst/ldst_input_record.py
index 8ba8f0255c8e7b62d6607360bd6a6cd32123773e..928ab9922f11f88a2a1b2120c5e31cacb94127bf 100644 (file)
--- a/src/soc/fu/ldst/ldst_input_record.py
+++ b/src/soc/fu/ldst/ldst_input_record.py
@@ -25,6 +25,7 @@ class CompLDSTOpSubset(CompOpSubsetBase):
                   ('is_signed', 1),
                   ('data_len', 4),
                   ('byte_reverse', 1),
+                  ('reserve', 1),     # atomic update
                   ('sign_extend', 1),
                   ('ldst_mode', LDSTMode),
                   ('insn', 32),