dumb syntax error

diff --git a/src/soc/fu/branch/main_stage.py b/src/soc/fu/branch/main_stage.py
index 76b00ea06e2af9b9989fe868e9673ec108b2739f..6efc5745b33e092dec40ac0036a36a9f68841cc5 100644 (file)
--- a/src/soc/fu/branch/main_stage.py
+++ b/src/soc/fu/branch/main_stage.py
@@ -89,7 +89,7 @@ class BranchMainStage(PipeModBase):
             comb += self.o.ctr.ok.eq(1)
             # take either all 64 bits or only 32 of post-incremented counter
             ctr_m = Signal(64, reset_less=True)
-            with m.If((op.is_32bit):
+            with m.If(op.is_32bit):
                 comb += ctr_m.eq(ctr[:32])
             with m.Else():
                 comb += ctr_m.eq(ctr)