more code-shuffle for TestMemoryPortInterface

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index b31014c559d3481c0e3aefa67b4d0a06628f4f71..b74eb82e2ca44bbadd0a868b38faa11df6998854 100644 (file)
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -136,23 +136,13 @@ class PortInterface(RecordObject):
                 ]
 
 
-class TestMemoryPortInterface(Elaboratable):
-    """TestMemoryPortInterface
-
-    This is a test class for simple verification of the LDSTCompUnit
-    and for the simple core, to be able to run unit tests rapidly and
-    with less other code in the way.
+class PortInterfaceBase(Elaboratable):
+    """PortInterfaceBase
 
-    Versions of this which are *compatible* (conform with PortInterface)
-    will include augmented-Wishbone Bus versions, including ones that
-    connect to L1, L2, MMU etc. etc. however this is the "base lowest
-    possible version that complies with PortInterface".
+    Base class for PortInterface-compliant Memory read/writers
     """
 
     def __init__(self, regwid=64, addrwid=4):
-        # hard-code memory addressing width to 6 bits
-        self.mem = TestMemory(regwid, 5, granularity=regwid//8,
-                              init=False)
         self.regwid = regwid
         self.addrwid = addrwid
         self.pi = PortInterface("ldst_port0", regwid, addrwid)
@@ -169,27 +159,15 @@ class TestMemoryPortInterface(Elaboratable):
     def connect_port(self, inport):
         return self.pi.connect_port(inport)
 
-    def set_wr_addr(self, m, addr):
-        m.d.comb += self.mem.wrport.addr.eq(addr)
-
-    def set_rd_addr(self, m, addr):
-        m.d.comb += self.mem.rdport.addr.eq(addr)
-
-    def set_wr_data(self, m, data, wen):
-        m.d.comb += self.mem.wrport.data.eq(data)  # write st to mem
-        m.d.comb += self.mem.wrport.en.eq(wen) # enable writes
-        return Const(1, 1)
-
-    def get_rd_data(self, m):
-        return self.mem.rdport.data, Const(1, 1)
+    def set_wr_addr(self, m, addr): pass
+    def set_rd_addr(self, m, addr): pass
+    def set_wr_data(self, m, data, wen): pass
+    def get_rd_data(self, m): pass
 
     def elaborate(self, platform):
         m = Module()
         comb, sync = m.d.comb, m.d.sync
 
-        # add TestMemory as submodule
-        m.submodules.mem = self.mem
-
         # state-machine latches
         m.submodules.st_active = st_active = SRLatch(False, name="st_active")
         m.submodules.ld_active = ld_active = SRLatch(False, name="ld_active")
@@ -307,4 +285,49 @@ class TestMemoryPortInterface(Elaboratable):
             yield from p.ports()
 
 
+class TestMemoryPortInterface(PortInterfaceBase):
+    """TestMemoryPortInterface
+
+    This is a test class for simple verification of the LDSTCompUnit
+    and for the simple core, to be able to run unit tests rapidly and
+    with less other code in the way.
+
+    Versions of this which are *compatible* (conform with PortInterface)
+    will include augmented-Wishbone Bus versions, including ones that
+    connect to L1, L2, MMU etc. etc. however this is the "base lowest
+    possible version that complies with PortInterface".
+    """
+
+    def __init__(self, regwid=64, addrwid=4):
+        super().__init__(regwid, addrwid)
+        # hard-code memory addressing width to 6 bits
+        self.mem = TestMemory(regwid, 5, granularity=regwid//8,
+                              init=False)
+
+    def set_wr_addr(self, m, addr):
+        m.d.comb += self.mem.wrport.addr.eq(addr)
+
+    def set_rd_addr(self, m, addr):
+        m.d.comb += self.mem.rdport.addr.eq(addr)
+
+    def set_wr_data(self, m, data, wen):
+        m.d.comb += self.mem.wrport.data.eq(data)  # write st to mem
+        m.d.comb += self.mem.wrport.en.eq(wen) # enable writes
+        return Const(1, 1)
+
+    def get_rd_data(self, m):
+        return self.mem.rdport.data, Const(1, 1)
+
+    def elaborate(self, platform):
+        m = super().elaborate(platform)
+
+        # add TestMemory as submodule
+        m.submodules.mem = self.mem
+
+        return m
+
+    def ports(self):
+        yield from super().ports()
+        # TODO: memory ports
+