nope. put it back and connect to platform pads in LS180Platform

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index df44741a586e6188e784fc0db88f101098b758da..f74b5f47d0159ddec0b4cbd909f174b8d9ab5bd1 100644 (file)
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -5,6 +5,8 @@ from migen import ClockSignal, ResetSignal, Signal, Instance, Cat
 from litex.soc.interconnect import wishbone as wb
 from litex.soc.cores.cpu import CPU
 
 from litex.soc.interconnect import wishbone as wb
 from litex.soc.cores.cpu import CPU
 

+from soc.debug.jtag import Pins, dummy_pinset # TODO move to suitable location
+from c4m.nmigen.jtag.tap import IOType

 
 from libresoc.ls180io import make_uart, make_gpio
 from litex.build.generic_platform import ConstraintManager
 
 from libresoc.ls180io import make_uart, make_gpio
 from litex.build.generic_platform import ConstraintManager


@@ -32,6 +34,56 @@ def make_wb_slave(prefix, obj):
         res['o_%s__%s' % (prefix, o)] = getattr(obj, o)
     return res
 
         res['o_%s__%s' % (prefix, o)] = getattr(obj, o)
     return res
 

+def make_pad(res, dirn, name, suffix, cpup, iop):
+    cpud, iod = ('i', 'o') if dirn else ('o', 'i')
+    res['%s_%s__core__%s' % (cpud, name, suffix)] = cpup
+    res['%s_%s__pad__%s' % (iod, name, suffix)] = iop
+
+
+def make_jtag_ioconn(res, pin, cpupads, iopads):
+    (fn, pin, iotype, pin_name, scan_idx) = pin
+    #serial_tx__core__o, serial_rx__pad__i,
+    print ("cpupads", cpupads)
+    print ("iopads", iopads)
+    print ("pin", fn, pin, iotype, pin_name)
+    cpu = cpupads[fn]
+    io = iopads[fn]
+    sigs = []
+
+    name = "%s_%s" % (fn, pin)
+
+    if iotype in (IOType.In, IOType.Out):
+        cpup = getattr(cpu, pin)
+        iop = getattr(io, pin)
+
+    if iotype == IOType.Out:
+        # output from the pad is routed through C4M JTAG and so
+        # is an *INPUT* into core.  ls180soc connects this to "real" peripheral
+        make_pad(res, True, name, "o", cpup, iop)
+
+    elif iotype == IOType.In:
+        # input to the pad is routed through C4M JTAG and so
+        # is an *OUTPUT* into core.  ls180soc connects this to "real" peripheral
+        make_pad(res, False, name, "i", cpup, iop)
+
+    elif iotype == IOType.InTriOut:
+        if fn == 'gpio': # sigh decode GPIO special-case
+            idx = int(pin[4:])
+        cpup, iop = cpu.i[idx], io.i[idx]
+        make_pad(res, False, name, "i", cpup, iop)
+        cpup, iop = cpu.o[idx], io.o[idx]
+        make_pad(res, True, name, "o", cpup, iop)
+        cpup, iop = cpu.oe[idx], io.oe[idx]
+        make_pad(res, True, name, "oe", cpup, iop)
+
+    if iotype in (IOType.In, IOType.InTriOut):
+        sigs.append(("i", 1))
+    if iotype in (IOType.Out, IOType.TriOut, IOType.InTriOut):
+        sigs.append(("o", 1))
+    if iotype in (IOType.TriOut, IOType.InTriOut):
+        sigs.append(("oe", 1))
+
+

 class LibreSoC(CPU):
     name                 = "libre_soc"
     human_name           = "Libre-SoC"
 class LibreSoC(CPU):
     name                 = "libre_soc"
     human_name           = "Libre-SoC"


@@ -159,6 +211,21 @@ class LibreSoC(CPU):
         if jtag_en:
             self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))
 
         if jtag_en:
             self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))
 

+        if variant == 'ls180':
+            # urr yuk.  have to expose iopads / pins from core to litex
+            # then back again.  cut _some_ of that out by connecting
+            self.padresources = (make_uart('uart', 0),
+                                 make_gpio('gpio', 0, 16))
+            self.pad_cm = ConstraintManager(self.padresources, [])
+            self.cpupads = {'uart': platform.request('uart', 0),
+                            'gpio': platform.request('gpio', 0)}
+            iopads = {'uart': self.pad_cm.request('uart', 0),
+                            'gpio': self.pad_cm.request('gpio', 0)}
+
+            p = Pins(dummy_pinset())
+            for pin in list(p):
+                make_jtag_ioconn(self.cpu_params, pin, self.cpupads, iopads)
+

         # add verilog sources
         self.add_sources(platform)
 
         # add verilog sources
         self.add_sources(platform)
 

diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index 469e4b4210f47b58a43a2791fce66ff01f534c67..50d2a95f9ff1bc781c112eb3ea0e78885c813693 100755 (executable)
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -8,6 +8,7 @@ from operator import or_
 from migen import (Signal, FSM, If, Display, Finish, NextValue, NextState,
                    Cat, Record, ClockSignal, wrap, ResetInserter)
 
 from migen import (Signal, FSM, If, Display, Finish, NextValue, NextState,
                    Cat, Record, ClockSignal, wrap, ResetInserter)
 

+from litex.build.generic_platform import Pins, Subsignal

 from litex.build.sim import SimPlatform
 from litex.build.io import CRG
 from litex.build.sim.config import SimConfig
 from litex.build.sim import SimPlatform
 from litex.build.io import CRG
 from litex.build.sim.config import SimConfig


@@ -31,7 +32,7 @@ from litex.soc.cores import uart
 from litex.tools.litex_sim import sdram_module_nphases, get_sdram_phy_settings
 
 from litex.tools.litex_sim import Platform
 from litex.tools.litex_sim import sdram_module_nphases, get_sdram_phy_settings
 
 from litex.tools.litex_sim import Platform

-from libresoc.ls180 import LS180Platform, io
+from libresoc.ls180 import LS180Platform

 
 from migen import Module
 from litex.soc.interconnect.csr import AutoCSR
 
 from migen import Module
 from litex.soc.interconnect.csr import AutoCSR


@@ -59,60 +60,6 @@ from litesdcard.core import SDCore
 from litesdcard.frontend.dma import SDBlock2MemDMA, SDMem2BlockDMA
 from litex.build.io import SDROutput, SDRInput
 
 from litesdcard.frontend.dma import SDBlock2MemDMA, SDMem2BlockDMA
 from litex.build.io import SDROutput, SDRInput
 

-from soc.debug.jtag import Pins, dummy_pinset # TODO move to suitable location
-from c4m.nmigen.jtag.tap import IOType
-from litex.build.generic_platform import ConstraintManager
-
-
-def make_pad(res, dirn, name, suffix, cpup, iop):
-    cpud, iod = ('i', 'o') if dirn else ('o', 'i')
-    res['%s_%s__core__%s' % (cpud, name, suffix)] = cpup
-    res['%s_%s__pad__%s' % (iod, name, suffix)] = iop
-
-
-def make_jtag_ioconn(res, pin, cpupads, iopads):
-    (fn, pin, iotype, pin_name, scan_idx) = pin
-    #serial_tx__core__o, serial_rx__pad__i,
-    print ("cpupads", cpupads)
-    print ("iopads", iopads)
-    print ("pin", fn, pin, iotype, pin_name)
-    cpu = cpupads[fn]
-    io = iopads[fn]
-    sigs = []
-
-    name = "%s_%s" % (fn, pin)
-
-    if iotype in (IOType.In, IOType.Out):
-        cpup = getattr(cpu, pin)
-        iop = getattr(io, pin)
-
-    if iotype == IOType.Out:
-        # output from the pad is routed through C4M JTAG and so
-        # is an *INPUT* into core.  ls180soc connects this to "real" peripheral
-        make_pad(res, True, name, "o", cpup, iop)
-
-    elif iotype == IOType.In:
-        # input to the pad is routed through C4M JTAG and so
-        # is an *OUTPUT* into core.  ls180soc connects this to "real" peripheral
-        make_pad(res, False, name, "i", cpup, iop)
-
-    elif iotype == IOType.InTriOut:
-        if fn == 'gpio': # sigh decode GPIO special-case
-            idx = int(pin[4:])
-        cpup, iop = cpu.i[idx], io.i[idx]
-        make_pad(res, False, name, "i", cpup, iop)
-        cpup, iop = cpu.o[idx], io.o[idx]
-        make_pad(res, True, name, "o", cpup, iop)
-        cpup, iop = cpu.oe[idx], io.oe[idx]
-        make_pad(res, True, name, "oe", cpup, iop)
-
-    if iotype in (IOType.In, IOType.InTriOut):
-        sigs.append(("i", 1))
-    if iotype in (IOType.Out, IOType.TriOut, IOType.InTriOut):
-        sigs.append(("o", 1))
-    if iotype in (IOType.TriOut, IOType.InTriOut):
-        sigs.append(("oe", 1))
-

 
 # I2C Master Bit-Banging --------------------------------------------------
 
 
 # I2C Master Bit-Banging --------------------------------------------------
 


@@ -396,24 +343,6 @@ class LibreSoCSim(SoCCore):
             )
         self.platform.name = "ls180"
 
             )
         self.platform.name = "ls180"
 

-        # Create link pads --------------------------------------------------
-
-        # urr yuk.  have to expose iopads / pins from core to litex
-        # then back again.  cut _some_ of that out by connecting
-        self.cpuresources = io()
-        self.padresources = io()
-        self.cpu_cm = ConstraintManager(self.cpuresources, [])
-        self.pad_cm = ConstraintManager(self.cpuresources, [])
-        self.cpupads = {'uart': self.cpu_cm.request('uart', 0),
-                        'gpio': self.cpu_cm.request('gpio', 0)}
-        self.iopads = {'uart': self.pad_cm.request('uart', 0),
-                        'gpio': self.pad_cm.request('gpio', 0)}
-
-        p = Pins(dummy_pinset())
-        for pin in list(p):
-            make_jtag_ioconn(self.cpu.cpu_params, pin, self.cpupads,
-                                                       self.iopads)
-

         # SDR SDRAM ----------------------------------------------
         if False: # not self.integrated_main_ram_size:
             self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
         # SDR SDRAM ----------------------------------------------
         if False: # not self.integrated_main_ram_size:
             self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))


@@ -485,7 +414,7 @@ class LibreSoCSim(SoCCore):
             self.specials += SDROutput(clk=sys_clk, i=sys_clk, o=sdr_clk)
 
         # UART
             self.specials += SDROutput(clk=sys_clk, i=sys_clk, o=sdr_clk)
 
         # UART

-        uart_core_pads = self.cpupads['uart']
+        uart_core_pads = self.cpu.cpupads['uart']

         self.submodules.uart_phy = uart.UARTPHY(
                 pads     = uart_core_pads,
                 clk_freq = self.sys_clk_freq,
         self.submodules.uart_phy = uart.UARTPHY(
                 pads     = uart_core_pads,
                 clk_freq = self.sys_clk_freq,


@@ -493,27 +422,16 @@ class LibreSoCSim(SoCCore):
         self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy,
                 tx_fifo_depth = 16,
                 rx_fifo_depth = 16))
         self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy,
                 tx_fifo_depth = 16,
                 rx_fifo_depth = 16))

-        # "real" pads connect to C4M JTAG iopad
-        uart_pads     = platform.request(uart_name) # "real" (actual) pin
-        uart_io_pads = self.iopads['uart'] # C4M JTAG pads
-        self.comb += uart_pads.tx.eq(uart_io_pads.tx)
-        self.comb += uart_io_pads.rx.eq(uart_pads.rx)

 
         self.csr.add("uart_phy", use_loc_if_exists=True)
         self.csr.add("uart", use_loc_if_exists=True)
         self.irq.add("uart", use_loc_if_exists=True)
 
         # GPIOs (bi-directional)
 
         self.csr.add("uart_phy", use_loc_if_exists=True)
         self.csr.add("uart", use_loc_if_exists=True)
         self.irq.add("uart", use_loc_if_exists=True)
 
         # GPIOs (bi-directional)

-        gpio_core_pads = self.cpupads['gpio']
+        gpio_core_pads = self.cpu.cpupads['gpio']

         self.submodules.gpio = GPIOTristateASIC(gpio_core_pads)
         self.add_csr("gpio")
 
         self.submodules.gpio = GPIOTristateASIC(gpio_core_pads)
         self.add_csr("gpio")
 

-        gpio_pads = platform.request("gpio") # "real" (actual) pins
-        gpio_io_pads = self.iopads['gpio'] # C4M JTAG pads
-        self.comb += gpio_io_pads.i.eq(gpio_pads.i)
-        self.comb += gpio_pads.o.eq(gpio_io_pads.o)
-        self.comb += gpio_pads.oe.eq(gpio_io_pads.oe)
-

         # SPI Master
         self.submodules.spi_master = SPIMaster(
             pads         = platform.request("spi_master"),
         # SPI Master
         self.submodules.spi_master = SPIMaster(
             pads         = platform.request("spi_master"),