author Luke Kenneth Casson Leighton Tue, 7 Apr 2020 18:11:36 +0000 (19:11 +0100) committer Luke Kenneth Casson Leighton Tue, 7 Apr 2020 18:11:36 +0000 (19:11 +0100)

@@ -161,7 +161,7 @@ class ISACaller:
# field-selectable versions of Condition Register TODO check bitranges?
self.crl = []
for i in range(8):
-            bits = tuple(range(i*4, (i+1)*4))# errr... maybe?
+            bits = tuple(range((7-i)*4, (8-i)*4))# errr... maybe?
_cr = FieldSelectableInt(self.cr, bits)
self.crl.append(_cr)
self.namespace["CR%d" % i] = _cr
index 558172bb61cf54664a99360969abec82075c7d1e..f072393d2f73594bb69eee16e91b1c279a2f98ea 100644 (file)
@@ -90,15 +90,20 @@ class DecoderTestCase(FHDLTestCase):
self.assertEqual(sim.gpr(3), SelectableInt(0x1000c, 64))

def test_mtcrf(self):
-        lst = ["addi 1, 0, 0xffffffff",
-               "mtcrf 1, 0x1",
-                               ]
-        with Program(lst) as program:
-            sim = self.run_tst_program(program)
-        print ("cr", sim.cr)
-        self.assertEqual(sim.cr, SelectableInt(0xf, 32))
-        print ("cr0", sim.crl[0])
-        self.assertTrue(SelectableInt(0xf, 4) == sim.crl[0])
+        for i in range(4):
+            # 0x7654 gives expected (3+4) (2+4) (1+4) (0+4) for i=3,2,1,0
+            lst = ["addi %d, 0, 0x7654" % (i+1),
+                   "mtcrf %d, %d" % (1<<i, i+1),
+                                   ]
+            with Program(lst) as program:
+                sim = self.run_tst_program(program)
+            print ("cr", sim.cr)
+            expected = (i+4)
+            # check CR itself
+            self.assertEqual(sim.cr, SelectableInt(expected<<(i*4), 32))
+            # check CR[0]/1/2/3 as well
+            print ("cr%d", sim.crl[i])
+            self.assertTrue(SelectableInt(expected, 4) == sim.crl[i])

def run_tst_program(self, prog, initial_regs=[0] * 32):
simulator = self.run_tst(prog, initial_regs)