comb on wr_index not sync

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 2b230fbab09a3caf3d71aa14e21bb7f24eff0d8e..c866f0248503e437a837d71420a71aabd30be02c 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -671,7 +671,7 @@ class ICache(Elaboratable):
         m_in = self.m_in
 
         wr_index = Signal(TLB_SIZE)
-        sync += wr_index.eq(hash_ea(m_in.addr))
+        comb += wr_index.eq(hash_ea(m_in.addr))
 
         with m.If(m_in.tlbie & m_in.doall):
             # Clear all valid bits