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passing LDSTException over to Trap Pipeline
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 6 Oct 2020 15:33:45 +0000
(16:33 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 6 Oct 2020 15:33:45 +0000
(16:33 +0100)
src/soc/decoder/decode2execute1.py
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src/soc/decoder/power_decoder2.py
patch
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src/soc/experiment/mem_types.py
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src/soc/fu/trap/trap_input_record.py
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diff --git
a/src/soc/decoder/decode2execute1.py
b/src/soc/decoder/decode2execute1.py
index cd4285be533d2c182a5c5102dda07940bee43bfe..9442af684b4bb8630021b5b48fd3f0f543c000a1 100644
(file)
--- a/
src/soc/decoder/decode2execute1.py
+++ b/
src/soc/decoder/decode2execute1.py
@@
-7,6
+7,7
@@
from nmigen import Signal, Record
from nmutil.iocontrol import RecordObject
from soc.decoder.power_enums import MicrOp, CryIn, Function, SPR, LDSTMode
from soc.consts import TT
from nmutil.iocontrol import RecordObject
from soc.decoder.power_enums import MicrOp, CryIn, Function, SPR, LDSTMode
from soc.consts import TT
+from soc.experiment.mem_types import LDSTException
class Data(Record):
class Data(Record):
@@
-50,6
+51,7
@@
class IssuerDecode2ToOperand(RecordObject):
self.oe = Data(1, "oe")
self.input_carry = Signal(CryIn, reset_less=True)
self.traptype = Signal(TT.size, reset_less=True) # trap main_stage.py
self.oe = Data(1, "oe")
self.input_carry = Signal(CryIn, reset_less=True)
self.traptype = Signal(TT.size, reset_less=True) # trap main_stage.py
+ self.ldst_exc = LDSTException("exc")
self.trapaddr = Signal(13, reset_less=True)
self.read_cr_whole = Data(8, "cr_rd") # CR full read mask
self.write_cr_whole = Data(8, "cr_wr") # CR full write mask
self.trapaddr = Signal(13, reset_less=True)
self.read_cr_whole = Data(8, "cr_rd") # CR full read mask
self.write_cr_whole = Data(8, "cr_wr") # CR full write mask
diff --git
a/src/soc/decoder/power_decoder2.py
b/src/soc/decoder/power_decoder2.py
index beab7bef52201939914aecbd69cce91b0015808e..b581922b01095f68d19906fcae7dc4969737e0a5 100644
(file)
--- a/
src/soc/decoder/power_decoder2.py
+++ b/
src/soc/decoder/power_decoder2.py
@@
-921,7
+921,7
@@
class PowerDecode2(PowerDecodeSubset):
#srr1(63 - 35) <= exc.perm_error; -- noexec fault
#srr1(63 - 44) <= exc.badtree;
#srr1(63 - 45) <= exc.rc_error;
#srr1(63 - 35) <= exc.perm_error; -- noexec fault
#srr1(63 - 44) <= exc.badtree;
#srr1(63 - 45) <= exc.rc_error;
- self.trap(m, TT.MEMEXC, 0x400)
+ self.trap(m, TT.MEMEXC, 0x400
, exc
)
with m.Else():
with m.If(exc.segment_fault):
self.trap(m, TT.MEMEXC, 0x380)
with m.Else():
with m.If(exc.segment_fault):
self.trap(m, TT.MEMEXC, 0x380)
@@
-981,7
+981,7
@@
class PowerDecode2(PowerDecodeSubset):
return m
return m
- def trap(self, m, traptype, trapaddr):
+ def trap(self, m, traptype, trapaddr
, exc=None
):
"""trap: this basically "rewrites" the decoded instruction as a trap
"""
comb = m.d.comb
"""trap: this basically "rewrites" the decoded instruction as a trap
"""
comb = m.d.comb
@@
-994,6
+994,7
@@
class PowerDecode2(PowerDecodeSubset):
comb += self.do_copy("fn_unit", Function.TRAP, True)
comb += self.do_copy("trapaddr", trapaddr >> 4, True) # bottom 4 bits
comb += self.do_copy("traptype", traptype, True) # request type
comb += self.do_copy("fn_unit", Function.TRAP, True)
comb += self.do_copy("trapaddr", trapaddr >> 4, True) # bottom 4 bits
comb += self.do_copy("traptype", traptype, True) # request type
+ comb += self.do_copy("ldst_exc", exc, True) # request type
comb += self.do_copy("msr", self.state.msr, True) # copy of MSR "state"
comb += self.do_copy("cia", self.state.pc, True) # copy of PC "state"
comb += self.do_copy("msr", self.state.msr, True) # copy of MSR "state"
comb += self.do_copy("cia", self.state.pc, True) # copy of PC "state"
diff --git
a/src/soc/experiment/mem_types.py
b/src/soc/experiment/mem_types.py
index c0523483108030d0b8594fa6695f6ab9e7216943..6eccb8454bf2c8d8c2bc0ddc70d311fdce4953f4 100644
(file)
--- a/
src/soc/experiment/mem_types.py
+++ b/
src/soc/experiment/mem_types.py
@@
-8,11
+8,10
@@
from nmigen import Signal
# https://bugs.libre-soc.org/show_bug.cgi?id=465
class LDSTException(RecordObject):
# https://bugs.libre-soc.org/show_bug.cgi?id=465
class LDSTException(RecordObject):
- _exc_types = ['alignment', 'instr_fault', 'invalid', 'badtree',
+ _exc_types = ['
happened', '
alignment', 'instr_fault', 'invalid', 'badtree',
'perm_error', 'rc_error', 'segment_fault',]
def __init__(self, name=None):
RecordObject.__init__(self, name=name)
'perm_error', 'rc_error', 'segment_fault',]
def __init__(self, name=None):
RecordObject.__init__(self, name=name)
- self.happened = Signal()
for f in self._exc_types:
setattr(self, f, Signal())
for f in self._exc_types:
setattr(self, f, Signal())
diff --git
a/src/soc/fu/trap/trap_input_record.py
b/src/soc/fu/trap/trap_input_record.py
index 7f9c51133dd38a9010cca201ab28123e1608f211..44fd5d6b51f249b19c123571927c56d1799c330e 100644
(file)
--- a/
src/soc/fu/trap/trap_input_record.py
+++ b/
src/soc/fu/trap/trap_input_record.py
@@
-19,11
+19,8
@@
class CompTrapOpSubset(CompOpSubsetBase):
('is_32bit', 1),
('traptype', TT.size), # see trap main_stage.py, PowerDecoder2
('trapaddr', 13),
('is_32bit', 1),
('traptype', TT.size), # see trap main_stage.py, PowerDecoder2
('trapaddr', 13),
+ ('ldst_exc', len(LDSTException._exc_types)),
]
]
- # add LDST field exception types
- #for f in LDSTException._exc_types:
- # layout.append((f, 1))
-
super().__init__(layout, name=name)
super().__init__(layout, name=name)