add MSR to simulator context

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index acc203c3758289754891c1afce3ba554f0d8b722..61aa451a1d10bbf72586d3d41ce28454d37e3f80 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -179,7 +179,7 @@ class ISACaller:
     # decoder2 - an instance of power_decoder2
     # regfile - a list of initial values for the registers
     def __init__(self, decoder2, regfile, initial_sprs=None, initial_cr=0,
-                       initial_mem=None):
+                       initial_mem=None, initial_msr=0):
         if initial_sprs is None:
             initial_sprs = {}
         if initial_mem is None:
@@ -188,6 +188,7 @@ class ISACaller:
         self.mem = Mem(initial_mem=initial_mem)
         self.pc = PC()
         self.spr = SPR(decoder2, initial_sprs)
+        self.msr = SelectableInt(initial_msr, 64) # underlying reg
         # TODO, needed here:
         # FPR (same as GPR except for FP nums)
         # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
@@ -215,6 +216,7 @@ class ISACaller:
                           'NIA': self.pc.NIA,
                           'CIA': self.pc.CIA,
                           'CR': self.cr,
+                          'MSR': self.msr,
                           'undefined': self.undefined,
                           'mode_is_64bit': True,
                           'SO': XER_bits['SO']

diff --git a/src/soc/decoder/pseudo/parser.py b/src/soc/decoder/pseudo/parser.py
index b05b9760bef832536cad4664622b29591a89ccaf..daf75df62fee6f431fec13cf76f29f3d2c27f96b 100644 (file)
--- a/src/soc/decoder/pseudo/parser.py
+++ b/src/soc/decoder/pseudo/parser.py
@@ -606,7 +606,7 @@ class PowerParser:
         name = p[1]
         if name in self.available_op_fields:
             self.op_fields.add(name)
-        if name in ['CR', 'LR', 'CTR', 'TAR', 'FPSCR']:
+        if name in ['CR', 'LR', 'CTR', 'TAR', 'FPSCR', 'MSR']:
             self.special_regs.add(name)
             self.write_regs.add(name) # and add to list to write
         p[0] = ast.Name(id=name, ctx=ast.Load())

diff --git a/src/soc/decoder/pseudo/pywriter.py b/src/soc/decoder/pseudo/pywriter.py
index 02ccce7f29abac36317542f53c798eb831a23758..465f366bdbf1214f5c5f4c606c464a533669435f 100644 (file)
--- a/src/soc/decoder/pseudo/pywriter.py
+++ b/src/soc/decoder/pseudo/pywriter.py
@@ -116,8 +116,8 @@ class PyISAWriter(ISA):
 
             classes = ', '.join(['ISACaller'] + self.pages_written)
             f.write('class ISA(%s):\n' % classes)
-            f.write('    def __init__(self, dec, regs, sprs, cr, mem):\n')
-            f.write('        super().__init__(dec, regs, sprs, cr, mem)\n')
+            f.write('    def __init__(self, dec, regs, sprs, cr, mem, msr):\n')
+            f.write('        super().__init__(dec, regs, sprs, cr, mem, msr)\n')
             f.write('        self.instrs = {\n')
             for page in self.pages_written:
                 f.write('            **self.%s_instrs,\n' % page)

diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py
index 0a728a043583e4bfcb7092863e7c5e777a491218..17b6d9587965d4fd2fe43f2739b448b28c42a71f 100644 (file)
--- a/src/soc/fu/cr/test/test_pipe_caller.py
+++ b/src/soc/fu/cr/test/test_pipe_caller.py
@@ -247,7 +247,8 @@ class TestRunner(FHDLTestCase):
                 print(test.name)
                 program = test.program
                 self.subTest(test.name)
-                sim = ISA(pdecode2, test.regs, test.sprs, test.cr)
+                sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
+                          test.msr)
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))
 

diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index 246a51e100367f3f786a220a4a688441051c22af..dc3cd9c3537dca5ebcf6ffa9cb35ff1f894b4b2c 100644 (file)
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -1,5 +1,6 @@
 class TestCase:
-    def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None):
+    def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
+                       msr=0):
 
         self.program = program
         self.name = name
@@ -14,3 +15,4 @@ class TestCase:
         self.sprs = sprs
         self.cr = cr
         self.mem = mem
+        self.msr = msr