indention

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index 40e73a3d9921dc499ca45a017299c93cfc0d784c..1e4177e4eac479b1f0d2bac32d508827377abe24 100644 (file)
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -189,22 +189,22 @@ class DataMerger(Elaboratable):
         self.data_i = Array(ul)
         self.data_o = DataMergerRecord()
 
-        def elaborate(self, platform):
-            m = Module()
-            comb = m.d.comb
-            #(1) pick a row
-            m.submodules.pick = pick = PriorityEncoder(self.array_size)
+    def elaborate(self, platform):
+        m = Module()
+        comb = m.d.comb
+        #(1) pick a row
+        m.submodules.pick = pick = PriorityEncoder(self.array_size)
+        for j in range(self.array_size):
+            comb += pick.i[j].eq(self.addr_match_i[j].bool())
+        valid = ~pick.n
+        idx = pick.o
+        #(2) merge
+        with m.If(valid):
+            l = []
             for j in range(self.array_size):
-                comb += pick.i[j].eq(self.addr_match_i[j].bool())
-            valid = ~pick.n
-            idx = pick.o
-            #(2) merge
-            with m.If(valid):
-                l = []
-                for j in range(self.array_size):
-                    select = self.addr_match_i[idx][j]
-                    l.append(Mux(select, self.data_i[j], 0))
-                comb += self.data_o.eq(ortreereduce(l))
+                select = self.addr_match_i[idx][j]
+                l.append(Mux(select, self.data_i[j], 0))
+            comb += self.data_o.eq(ortreereduce(l))
 
 
 class LDSTPort(Elaboratable):